(57) ABSTRACT A method is provided for operating a NAND array that includes a plurality of
blocks of memory cells. A block of memory cells in the plurality of blocks includes a plurality …

BACKGROUND The present disclosure relates to computer memory, and more specifically,
to solid state drives (SSDs). SSDs are increasingly being used in modern computers, often …

Memory systems may include a memory including a plu rality of blocks, and a controller
suitable for counting, with a counter, a number of reads to a block of the plurality of blocks …

A non-volatile memory is configured to allow programming and erase at the sub-block level.
In a sub-block erase, some of the memory cells can be selected for erase while others are …

In one embodiment, the method includes performing a read operation on a memory, and
determining, by a memory controller, whether to perform a reliability verification read …

(US) 7.495, 954 B2 2, 2009 to 7,804,718 B2 9/2010 Kim cr 7,808,831 B2 10/2010 Mokhlesi
et al.(*) Notice: Subject to any disclaimer, the term of this 7,818,525 B1 10/2010 Frost et al …

(57) ABSTRACT A method of operating a storage device having a nonvolatile memory
including at least one memory block having a plurality of Sub-blocks includes reading …

BACKGROUND 1. Field Embodiments described herein relate to a semiconductor memory
device. 2. Description of the Related Art Flash memory is an example of semiconductor …

An erase operation includes one or more erase depth checks to detect the occurrence of
shallow erased memory cells at the end of an erase process. Memory cells are subjected to …

A method includes adjusting a counter value to indicate an access operation to a first portion
of a non-volatile memory. The access operation is an erase operation or a write operation …