Methods of fabricating a capped interconnect for a microelectronic device which includes a
sealing feature for any gaps between a capping layer and an interconnect and structures …

6,028,362 A* 2/2000 Omura 6,037,664 A 3/2000 Zhao et al. 6,069,068 A 5/2000 Rathore et
al. 6,130,161 A 10/2000 Ashley et al. 6,258.659 B1* 7/2001 Gruening et al. 6.258, 710 B1 …

Zafman LLP (57) ABSTRACT Multiple level interconnect structures and methods for fab
ricating the interconnect Structures are disclosed. The inter connect Structures may contain …

(57) ABSTRACT A method comprising introducing an interconnect structure in an opening
through a dielectric over a contact point, and introducing a conductive shunt material …

Many integrated circuits contain multi-layer electrical interconnect Structures to provide
electrical Signals to logic elements Such as transistors located on a Semiconductor …

Some embodiments can include a method of manufacturing first electronic device (s) and
second electronic device (s), the method including: providing a carrier Substrate having a …

A method of creating metal caps on copper lines within an inter-line dielectric (ILD) deposits
a thin (eg, 5 nm) metal blanket film (eg, Ta/TaN) on top the copper lines and dielectric, after …

An apparatus including a substrate comprising a device having contact point; a dielectric
layer overlying the device with an opening to the contact point; and an interconnect structure …

Method of manufacturing a structure which includes the steps of providing a structure having
an insulator layer with at least one interconnect, forming a sub lithographic template mask …

PCT/US2011/037207, filed on May 19, 2011. devices including providing a carrier Substrate
having a first (60) Provisional application No. 61/383,600, filed on Sep. side, a. second side …