Compute-in-memory chips for deep learning: Recent trends and prospects
Compute-in-memory (CIM) is a new computing paradigm that addresses the memory-wall
problem in hardware accelerator design for deep learning. The input vector and weight …
problem in hardware accelerator design for deep learning. The input vector and weight …
A 40-nm MLC-RRAM compute-in-memory macro with sparsity control, on-chip write-verify, and temperature-independent ADC references
Resistive random access memory (RRAM)-based compute-in-memory (CIM) has shown
great potential for accelerating deep neural network (DNN) inference. However, device …
great potential for accelerating deep neural network (DNN) inference. However, device …
A 40nm RRAM compute-in-memory macro featuring on-chip write-verify and offset-cancelling ADC references
Resistive random access memory (RRAM) based compute-in-memory (CIM) has shown
great potentials for deep neural network (DNN) inference. Prior works generally used off …
great potentials for deep neural network (DNN) inference. Prior works generally used off …
Ferroelectric tunnel junction based crossbar array design for neuro-inspired computing
Ferroelectric tunnel junction (FTJ) based crossbar array is a promising candidate for the
implementation of low-power and area-efficient neuro-inspired computing. In this paper, we …
implementation of low-power and area-efficient neuro-inspired computing. In this paper, we …
SOT-MRAM digital PIM architecture with extended parallelism in matrix multiplication
Emerging device-based digital processing-in-memory (PIM) architectures have been
actively studied due to their energy and area efficiency derived from analog to digital …
actively studied due to their energy and area efficiency derived from analog to digital …
AILC: Accelerate on-chip incremental learning with compute-in-memory technology
As AI applications become pervasive on edge device, incrementally learning new tasks is
demanded for deep neural network (DNN) models. In this article, we proposed AILC, a …
demanded for deep neural network (DNN) models. In this article, we proposed AILC, a …
Design-time Reference Current Generation for Robust Spintronic-based Neuromorphic Architecture
ST Ahmed, M Mayahinia, M Hefenbrock… - ACM Journal on …, 2023 - dl.acm.org
Neural Networks (NN) can be efficiently accelerated in a neuromorphic fabric based on
emerging resistive non-volatile memories (NVM), such as Spin Transfer Torque Magnetic …
emerging resistive non-volatile memories (NVM), such as Spin Transfer Torque Magnetic …
H3D-Transformer: A Heterogeneous 3D (H3D) Computing Platform for Transformer Model Acceleration on Edge Devices
Prior hardware accelerator designs primarily focused on single-chip solutions for 10 MB-
class computer vision models. The GB-class transformer models for natural language …
class computer vision models. The GB-class transformer models for natural language …
Process and runtime variation robustness for spintronic-based neuromorphic fabric
ST Ahmed, M Mayahinia, M Hefenbrock… - 2022 IEEE European …, 2022 - ieeexplore.ieee.org
Neural Networks (NN) can be efficiently accelerated using emerging resistive non-volatile
memories (eNVM), such as Spin Transfer Torque Magnetic RAM (STT-MRAM). However …
memories (eNVM), such as Spin Transfer Torque Magnetic RAM (STT-MRAM). However …
Sparsity-Oriented MRAM-Centric Computing for Efficient Neural Network Inference
Near-memory computing (NMC) and in-memory computing (IMC) paradigms show great
importance in non-von Neumann architecture. Spin-transfer torque magnetic random access …
importance in non-von Neumann architecture. Spin-transfer torque magnetic random access …