Compiler, compiler apparatus and compilation method

T Heishi, T Sakata, H Ogawa, R Miyachi… - US Patent …, 2012 - Google Patents
An operator definition file 102 and the like included in a source program 101 and a compiler
100 that translates the Source program 101 into a machine language program 105 are …

Coalescing adjacent gather/scatter operations

AT Forsyth, BJ Hickmann, JC Hall… - US Patent 9,348,601, 2016 - Google Patents
According to one embodiment, a processor includes an instruction decoder to decode a first
instruction to gather data elements from memory, the first instruction having a first operand …

Method and apparatus for embedding wide instruction words in a fixed-length instruction set architecture

E Altman, M Gschwind, D Prener, J Rivers… - US Patent App. 11 …, 2006 - Google Patents
(US): Sumedh W. Sathaye Cary, NC ing of conventional and augmented instructions within
an (US). John-David Wellman. Hop ewell instruction stream, wherein control may be directly …

Method and apparatus to vectorize multiple input instructions

Y Almog, R Rosner, R Ronen - US Patent 7,802,076, 2010 - Google Patents
An optimization unit to search for two or more candidate instructions in an instruction trace
and to merge the two or more candidate instructions into a single instruction with multiple …

System and method for fusing instructions queued during a time window defined by a delay counter

I Ouziel, L Rappoport, R Valentine, R Gabor… - US Patent …, 2017 - Google Patents
(57) ABSTRACT A technique to enable efficient instruction fusion within a computer system
is disclosed. In one embodiment, processor logic delays the processing of a first instruction …

Software source transfer selects instruction word sizes

TT Hahn, EJ Stotzer, MD Asal - US Patent 7,581,082, 2009 - Google Patents
This invention employs a 16-bit instruction set that has a subset of the functionality of the 32-
bit instruction set. In this invention 16-bit instructions and 32-bit instructions can coex ist in …

Packet processor and packet processor system

K Abiru, T Tsuruoka - US Patent App. 10/124,828, 2003 - Google Patents
In a packet processor and a packet processor system for performing predetermined packet
processing for an inputted packet in a packet relaying apparatus or the like, a packet data …

Deinterleave strided data elements processors, methods, systems, and instructions

M Plotnikov, E Ould-Ahmed-Vall - US Patent 10,191,740, 2019 - Google Patents
A method performed by a processor includes receiving an instruction. The instruction
indicating a source operand, indicating a stride, indicating at least one set of strided data …

Coalescing adjacent gather/scatter operations

AT Forsyth, BJ Hickmann, JC Hall… - US Patent 9,632,792, 2017 - Google Patents
According to one embodiment, a processor includes an instruction decoder to decode a first
instruction to gather data elements from memory, the first instruction having a first operand …

Coalescing adjacent gather/scatter operations

AT Forsyth, BJ Hickmann, JC Hall… - US Patent 9,575,765, 2017 - Google Patents
According to one embodiment, a processor includes an instruction decoder to decode a first
instruction to gather data elements from memory, the first instruction having a first operand …