Frequency multiplier using phase-locked loop
HG Shettar, S Kotabagi, N Shanbhag… - 2020 IEEE 17th India …, 2020 - ieeexplore.ieee.org
A Phase-Locked Loop (PLL) Frequency multiplier application is been presented in this
paper. The designed PLL is a type-2, order-3 CPPLL with a tuning range of 143-176M Hz …
paper. The designed PLL is a type-2, order-3 CPPLL with a tuning range of 143-176M Hz …
Analysis of deadbeat control for an integer-N charge-pump PLL
A Koithyar, TK Ramesh - Procedia Computer Science, 2015 - Elsevier
The conventional method to decrease the settling time of oscillators is to increase the
bandwidth, which in turn results in an increase in the spur content, affecting the transient …
bandwidth, which in turn results in an increase in the spur content, affecting the transient …
A new fast locking charge pump PLL: analysis and design
VS Sadeghi, H Miar-Naimi - Analog Integrated Circuits and Signal …, 2013 - Springer
In this paper a new structure for a fast locking charge pump phase locked loop (CPPLL) is
introduced which overcomes the trade-off between the settling time and overshoot of the …
introduced which overcomes the trade-off between the settling time and overshoot of the …
[PDF][PDF] Power packet dispatching based on synchronization with features on safety
Y Zhou - 2015 - repository.kulib.kyoto-u.ac.jp
In the context of liberalized power market, the environment of power systems at present is
more decentralized than that of conventional ones. Accordingly, the power distribution and …
more decentralized than that of conventional ones. Accordingly, the power distribution and …
[PDF][PDF] A Fast Locking Digital Phase-Locked Loop using Frequency Difference Stage
MA Ahmed, HA Shawkey, HA Elsemary… - International Journal of …, 2014 - academia.edu
Phase-Locked Loop (PLL) is one of the most important synchronizing circuits used in
transceivers, communication systems, etc. Conventional digital PLL (DPLL) should be …
transceivers, communication systems, etc. Conventional digital PLL (DPLL) should be …
A new analytical approach to predicting cycle-slipping in charge pump PLLs
V Sadat Sadeghi, H Miar Naimi - COMPEL: The International Journal …, 2013 - emerald.com
Purpose–The linear analysis presented for the charge pump phase locked loops (CPPLLs)
becomes inaccurate or incorrect where cycle slipping occurs. In this paper, an analytical …
becomes inaccurate or incorrect where cycle slipping occurs. In this paper, an analytical …
A new frequency comparator for using in fast charge pump PLLs
VS Sadeghi, HM Naimi - 2013 21st Iranian Conference on …, 2013 - ieeexplore.ieee.org
A bang-bang frequency comparator (BBFC) can be used in the feedthrough path in pump
phase locked loops (CPPLL) to increase the locking speed. In this paper, we present a new …
phase locked loops (CPPLL) to increase the locking speed. In this paper, we present a new …