The appearance of radix-2 2 was a milestone in the design of pipelined FFT hardware
architectures. Later, radix-2 2 was extended to radix-2 k. However, radix-2 k was only …

The field of pipelined FFT hardware architectures has been studied during the last 50 years.
This paper is a survey that includes the main advances in the field related to architectures for …

This paper presents a novel approach to develop parallel pipelined architectures for the fast
Fourier transform (FFT). A formal procedure for designing FFT architectures using folding …

This brief presents a novel 4096-point radix-4 memory-based fast Fourier transform (FFT).
The proposed architecture follows a conflict-free strategy that only requires a total memory of …

In this paper, we present a systematic approach to design hardware circuits for bit-
dimension permutations. The proposed approach is based on decomposing any bit …

In this paper, we present new feedforward FFT hardware architectures based on rotator
allocation. The rotator allocation approach consists in distributing the rotations of the FFT in …

This brief presents novel circuits for calculating bit reversal on a series of data. The circuits
are simple and consist of buffers and multiplexers connected in series. The circuits are …

This paper presents a novel 64-parallel 4096-point radix-2 memory-based fast Fourier
transform (FFT) architecture for 6G. This approach is the first one to use 64 parallel branches …

The fast Fourier transform (FFT) is a widely used algorithm in signal processing applications.
FFT hardware architectures are designed to meet the requirements of the most demanding …

This paper presents a 512-point feedforward FFT architecture for wireless personal area
network (WPAN). The architecture processes a continuous flow of 8 samples in parallel …