[图书][B] Power-aware testing and test strategies for low power devices
Managing the power consumption of circuits and systems is now considered one of the most
important challenges for the semiconductor industry. Elaborate power management …
important challenges for the semiconductor industry. Elaborate power management …
[图书][B] Design of 3D integrated circuits and systems
R Sharma - 2018 - books.google.com
Three-dimensional (3D) integration of microsystems and subsystems has become essential
to the future of semiconductor technology development. 3D integration requires a greater …
to the future of semiconductor technology development. 3D integration requires a greater …
Capture power reduction using clock gating aware test generation
K Chakravadhanula, V Chickermane… - 2009 International …, 2009 - ieeexplore.ieee.org
Scan-based manufacturing test of low power designs often exceeds the very tight functional
constraints on average and instantaneous logic switching. The logic activity during the shift …
constraints on average and instantaneous logic switching. The logic activity during the shift …
Test mode isolation and power reduction in embedded core-based digital systems of integrated circuits (ICs) with multiple power domains
GK Ge, R Kashyap - US Patent 10,310,013, 2019 - Google Patents
Embodiments include a power isolation circuit. The power isolation circuit includes a logic
block, a wrapper cell, an isolation cell, a test control unit, and/or a power control unit. The …
block, a wrapper cell, an isolation cell, a test control unit, and/or a power control unit. The …
On testing timing-speculative circuits
By allowing the occurrence of infrequent timing errors and correcting them online, circuit-
level timing speculation is one of the most promising variation-tolerant design techniques …
level timing speculation is one of the most promising variation-tolerant design techniques …
An evaluation method for panoramic understanding of programming by comparison with visual examples
DM Calderon, K Man, H Kiyomitsu… - 2015 IEEE Frontiers …, 2015 - ieeexplore.ieee.org
In recent years, professionals in different fields have become able to do programming by
using simplified software tools, as a consequence of this they are becoming able to …
using simplified software tools, as a consequence of this they are becoming able to …
Low Power Testing—What Can Commercial Design-for-Test Tools Provide?
X Lin - Journal of Low Power Electronics and Applications, 2011 - mdpi.com
Minimizing power consumption during functional operation and during manufacturing tests
has become one of the dominant requirements for the semiconductor designs in the past …
has become one of the dominant requirements for the semiconductor designs in the past …
Test of power management structures
M Kassab, M Tehranipoor - Power-Aware Testing and Test Strategies for …, 2010 - Springer
Shrinking technology nodes offer higher levels of integration and better performance.
However, they are accompanied by increased dynamic (switching) and static (leakage) …
However, they are accompanied by increased dynamic (switching) and static (leakage) …
Clock tree construction using gated clock cloning
WH Chen, HH Chang, JH Hung… - 2012 4th Asia …, 2012 - ieeexplore.ieee.org
Clock gating is one of the important techniques to achieve low power and small area in high-
performance synchronous circuit design. In this paper, we propose a three-phase clock …
performance synchronous circuit design. In this paper, we propose a three-phase clock …
Design of a reliable power delivery network for monolithic 3D ICs
SC Hung, K Chakrabarty - 2020 Design, Automation & Test in …, 2020 - ieeexplore.ieee.org
As Moore's law hits physical limits, monolithic 3D (M3D) integration based on fine-grained
monolithic inter-tier vias is emerging as a promising technique to continue performance …
monolithic inter-tier vias is emerging as a promising technique to continue performance …