A reconfigurable 16/32 Gb/s dual-mode NRZ/PAM4 SerDes in 65-nm CMOS

A Roshan-Zamir, O Elhadidy, HW Yang… - IEEE Journal of Solid …, 2017 - ieeexplore.ieee.org
While four-level pulse amplitude modulation (PAM4) standards are emerging to increase
bandwidth density, the majority of standards use simple binary non-returnto-zero (NRZ) …

Recent Advances in Ultra-High-Speed Wireline Receivers With ADC-DSP-Based Equalizers

S Jang, J Lee, Y Choi, D Kim… - IEEE Open Journal of the …, 2024 - ieeexplore.ieee.org
High-speed wireline data transceivers (TRX) with analog-to-digital converter (ADC) followed
by digital signal processor (DSP) on the receiver (RX) equalizer became popular for …

A 20 Gb/s CMOS optical receiver with limited-bandwidth front end and local feedback IIR-DFE

A Sharif-Bakhtiar, AC Carusone - IEEE Journal of Solid-State …, 2016 - ieeexplore.ieee.org
Implementation of highly integrated optical receivers in CMOS promises low cost, but
combining high gain, low noise, high bandwidth, and low power in a CMOS transimpedance …

A 0.41 pJ/Bit 10 Gb/s hybrid 2 IIR and 1 discrete-time DFE tap in 28 nm-LP CMOS

S Shahramian, AC Carusone - IEEE Journal of Solid-State …, 2015 - ieeexplore.ieee.org
An ideal infinite impulse response (IIR) decision feedback equalizer (DFE) can have an
effect on wireline received waveforms similar to a continuous-time equalizer, but without the …

A 1-V 10-Gb/s/pin single-ended transceiver with controllable active-inductor-based driver and adaptively calibrated cascaded-equalizer for post-LPDDR4 interfaces

J Song, S Hwang, HW Lee… - IEEE Transactions on …, 2017 - ieeexplore.ieee.org
A 1-V 10-Gb/s/pin single-ended transceiver with a controllable active inductor-based output
driver and adaptively calibrated cascaded-equalizer with infinite impulse response and finite …

A 32 gb/s 0.55 mw/gbps pam4 1-fir 2-iir tap dfe receiver in 65-nm cmos

O Elhadidy, A Roshan-Zamir, HW Yang… - 2015 symposium on …, 2015 - ieeexplore.ieee.org
A PAM4 serial I/O receiver efficiently implements a decision feedback equalizer (DFE) that
employs 1-FIR and 2-IIR taps for first post-cursor and long-tail ISI cancellation, respectively …

Edge-Based Adaptation for a 1 IIR + 1 Discrete-Time Tap DFE Converging in s

S Shahramian, B Dehlaghi… - IEEE Journal of Solid …, 2016 - ieeexplore.ieee.org
A 16 Gb/s 1-tap Infinite impulse response (IIR)+ 1-tap discrete-time (DT) decision feedback
equalizer (DFE) with integrated clock recovery and adaptation is demonstrated in 28 nm FD …

A 0.31-pJ/bit 20-Gb/s DFE with 1 discrete tap and 2 IIR filters feedback in 40-nm-LP CMOS

KY Chen, WY Chen, SI Liu - … on Circuits and Systems II: Express …, 2016 - ieeexplore.ieee.org
This brief presents a low-power 20-Gb/s decision feedback equalizer (DFE) with one
discrete tap and two infinite impulse response (IIR) filters feedback. The advantage of the IIR …

A 30-Gb/s 1.37-pJ/b CMOS receiver for optical interconnects

Q Pan, Y Wang, Z Hou, L Sun, Y Lu… - Journal of Lightwave …, 2014 - ieeexplore.ieee.org
This paper presents a digitally controlled 1-V 30-Gb/s 1.37-pJ/b optical receiver in 65-nm
CMOS technology. This receiver consists of an inverter-based inductive transimpedance …

A 0.002-mm 6.4-mW 10-Gb/s Full-Rate Direct DFE Receiver With 59.6% Horizontal Eye Opening Under 23.3-dB Channel Loss at Nyquist Frequency

Y Chen, PI Mak, L Zhang… - IEEE Transactions on …, 2014 - ieeexplore.ieee.org
This paper reports a full-rate direct decision-feedback-equalization (DFE) receiver with
circuit techniques to widen the data eye opening with competitive power and area …