Well-designed circuits are one key ldquoinsulatingrdquo layer between the increasingly
unruly behavior of scaled complementary metal-oxide-semiconductor devices and the …

This paper reviews the design challenges that current and future processors must face, with
stringent power limits, high-frequency targets, and the continuing system integration trends …

Due to shrinking technologies and increasing design sizes, it is becoming more difficult and
expensive to distribute a global clock signal with low skew throughout a processor die …

The IBM POWER4 processor is a 174-million-transistor chip that runs at a clock frequency of
greater than 1.3 GHz. It contains two microprocessor cores, high-speed buses, and an on …

This paper analyzes the impact of power-supply noise on the performance of high-frequency
microprocessors. First, delay models that take this noise into account are proposed for …

Today's networks of processors on and off chip, operating with independent clocks, need
effective synchronization of the data passing between them for reliability. When two or more …

A 5th generation SPARC64 processor is fabricated in 130nm SOI CMOS process with 8
layers of Cu metallization. It runs at 1.3 GHz with 34.7 W power dissipation in the laboratory …

With increasing integration densities, large chip designs are commonly partitioned into
multiple clock domains. While the computation within each individual domain may be …

A global clock network that incorporates standing waves and coupled oscillators to distribute
a high-frequency clock signal with low skew and low jitter is described. The key design …

This paper reviews the status of present day on-chip wiring design methodologies and
understanding. A brief explanation is given of the fundamental transmission-line properties …