IBM Power9 processor architecture

SK Sadasivam, BW Thompto, R Kalla, WJ Starke - IEEE Micro, 2017 - ieeexplore.ieee.org
The IBM Power9 processor has an enhanced core and chip architecture that provides
superior thread performance and higher throughput. The core and chip architectures are …

Conditional speculation: An effective approach to safeguard out-of-order execution against spectre attacks

P Li, L Zhao, R Hou, L Zhang… - 2019 IEEE international …, 2019 - ieeexplore.ieee.org
Speculative execution side-channel vulnerabilities such as Spectre reveal that conventional
architecture designs lack security consideration. This paper proposes a software transparent …

Transactional memory support in the IBM POWER8 processor

HQ Le, GL Guthrie, DE Williams… - IBM Journal of …, 2015 - ieeexplore.ieee.org
With multi-core processors, parallel programming has taken on greater importance.
Traditional parallel programming techniques based on critical sections controlled by locking …

Moore's law at 50: Are we planning for retirement?

G Yeric - 2015 IEEE International Electron Devices Meeting …, 2015 - ieeexplore.ieee.org
The Moore's Law era enjoyed a long run of lithographically-enabled pitch shrinking that
directly reduced the cost per (von Neumann) function, as well as system power and …

CRISP: critical slice prefetching

H Litz, G Ayers, P Ranganathan - Proceedings of the 27th ACM …, 2022 - dl.acm.org
The high access latency of DRAM continues to be a performance challenge for
contemporary microprocessor systems. Prefetching is a well-established technique to …

The cache and memory subsystems of the IBM POWER8 processor

WJ Starke, J Stuecheli, DM Daly… - IBM Journal of …, 2015 - ieeexplore.ieee.org
In this paper, we describe the IBM POWER8™ cache, interconnect, memory, and
input/output subsystems, collectively referred to as the “nest.” This paper focuses on the …

A case study for performance portability using OpenMP 4.5

R Gayatri, C Yang, T Kurth, J Deslippe - … Dallas, TX, USA, November 11-17 …, 2019 - Springer
In recent years, the HPC landscape has shifted away from traditional multi-core CPU
systems to energy-efficient architectures, such as many-core CPUs and accelerators like …

Enabling scalable chiplet-based uniform memory architectures with silicon photonics

P Fotouhi, S Werner, J Lowe-Power… - Proceedings of the …, 2019 - dl.acm.org
Chiplet-based systems have recently received much attention for scaling-up processing
power in HPC systems due to their high energy efficiency and low cost manufacturing; …

Design of efficient BCD adders in quantum-dot cellular automata

G Cocorullo, P Corsonello, F Frustaci… - IEEE Transactions on …, 2016 - ieeexplore.ieee.org
Among the emerging technologies recently proposed as alternatives to the classic CMOS,
quantum-dot cellular automata (QCA) is one of the most promising solutions to design …

D-oram: Path-oram delegation for low execution interference on cloud servers with untrusted memory

R Wang, Y Zhang, J Yang - 2018 IEEE International …, 2018 - ieeexplore.ieee.org
Cloud computing has evolved into a promising computing paradigm. However, it remains a
challenging task to protect application privacy and, in particular, the memory access …