An asynchronous design paradigm is capable of addressing the impact of increased
process variability, power and thermal bottlenecks, high fault rates, aging, and scalability …

Technical publications often make either subjective or unsubstantiated claims about today's
functional verification process---such as, 70 percent of a project's overall effort is spent in …

This book is an introduction to the design of asynchronous circuits. It is an updated and
significantly extended version of an eight-chapter tutorial that first appeared as Part I in the …

Modern computing devices, ranging from smartphones and tablets up to powerful servers,
rely on complex silicon chips that integrate inside them hundreds or thousands of …

Top-Down VLSI Design: From Architectures to Gate-Level Circuits and FPGAs represents a
unique approach to learning digital design. Developed from more than 20 years teaching …

This paper investigates the metastability of true single-phase clock (TSPC) D flip flops
(DFFs) and its impact on the resolution of Vernier time-to-digital converters (TDCs). The …

Time-mode circuits, where information is represented by time difference between digital
events, offer a viable and technology-friendly means to realize mixed-mode circuits and …

A high-resolution time-to-digital converter (TDC) implemented with field programmable gate
array (FPGA) based on delay wrapping and averaging is presented. The fundamental idea …

Better-Than-Worst-Case-Designs use timing speculation to run with a cycle period faster
than the one required for worst-case conditions. This speculation may produce timing …

In modern CMOS processes, soft errors and metastability are two prominent failure
mechanisms. Radiation induced single event upsets, or soft-errors, have become a …