Provided is an electric signal transmission device which corrects a data error caused by data
transition in a pulse amplitude modulation signal to increase an EYE width. The electric …

A circuit and corresponding method for dynamic voltage frequency scaling (DVFS) on a chip
employ a delay-locked loop (DLL)-based clocking architecture. The circuit comprises a DLL …

A receiver is provided that includes a time-to-digital con verter for converting a phase
difference between a clock signal and a received data signal into a phase-difference digital …

(57) ABSTRACT A method for a slave device for calibrating an output timing for transmitting
data to a master device is provided. The master and slave devices are communicatively …

Embodiments of the disclosure are drawn to apparatuses and methods for drivers with
reduced voltage no?? signals may be provided to semiconductor devices, and may be …

In an embodiment, a method includes filtering, with a low-pass filter, a voltage signal (Vdd)
of a chip to create a filtered signal (Vref). The method further includes dividing Vref by a …

A delay-locked loop (DLL) and corresponding method improve frequency of a chip. The DLL
comprises a first programmable delay element configured to output a first clock, a second …

Embodiments of the disclosure are drawn to apparatuses and methods for drivers with
reduced voltage noise. Clock signals may be provided to semiconductor devices, and may …

A circuit detects a voltage droop exhibited by a power supply. A first signal delay line outputs
a first delayed signal, and is comprised of delay elements having a first threshold voltage. A …

In an embodiment, a method includes initializing an input clock rotating register by sending
a reset signal synchro nized to an input clock signal and initializing an output clock rotating …