Modern development methods and tools for embedded reconfigurable systems: A survey

L Jóźwiak, N Nedjah, M Figueroa - Integration, 2010 - Elsevier
Heterogeneous reconfigurable systems provide drastically higher performance and lower
power consumption than traditional CPU-centric systems. Moreover, they do it at much lower …

Measurements of extremely low radioactivity levels in BOREXINO

C Arpesella, HO Back, M Balata, T Beau, G Bellini… - Astroparticle …, 2002 - Elsevier
The techniques researched, developed and applied towards the measurement of
radioisotope concentrations at ultra-low levels in the real-time solar neutrino experiment …

Machine learning predictive modelling high-level synthesis design space exploration

BC Schafer, K Wakabayashi - IET computers & digital techniques, 2012 - IET
A machine learning-based predictive model design space exploration (DSE) method for
high-level synthesis (HLS) is presented. The method creates a predictive model for a …

Divide and conquer high-level synthesis design space exploration

BC Schafer, K Wakabayashi - ACM Transactions on Design Automation …, 2012 - dl.acm.org
A method to accelerate the Design Space Exploration (DSE) of behavioral descriptions for
high-level synthesis based on a divide and conquer method called Divide and Conquer …

Adaptive simulated annealer for high level synthesis design space exploration

BC Schafer, T Takenaka… - … Symposium on VLSI …, 2009 - ieeexplore.ieee.org
This paper presents a microarchitectural design space exploration tool called cwbexplorer
based on an Adpative Simulated Annealer Exploration Algorithm (ASA-ExpA) for behavioral …

[图书][B] Compilation techniques for reconfigurable architectures

JMP Cardoso, PC Diniz - 2011 - books.google.com
The extreme? exibility of recon? gurable architectures and their performance pot-tial have
made them a vehicle of choice in a wide range of computing domains, from rapid circuit …

Probabilistic multiknob high-level synthesis design space exploration acceleration

BC Schafer - IEEE Transactions on Computer-Aided Design of …, 2015 - ieeexplore.ieee.org
One of the biggest advantages of C-based very large scale integration design over
traditional register transfer level is its ability to automatically generate architectures with …

Multilevel granularity parallelism synthesis on FPGAs

A Papakonstantinou, Y Liang… - 2011 IEEE 19th …, 2011 - ieeexplore.ieee.org
Recent progress in High-Level Synthesis (HLS) techniques has helped raise the abstraction
level of FPGA programming. However implementation and performance evaluation of the …

ASC: a stream compiler for computing with FPGAs

O Mencer - IEEE Transactions on Computer-Aided Design of …, 2006 - ieeexplore.ieee.org
A stream compiler (ASC) for computing with field programmable gate arrays (FPGAs)
emerges from the ambition to bridge the hardware-design productivity gap where the …

Design space pruning through early estimations of area/delay tradeoffs for FPGA implementations

S Bilavarn, G Gogniat, JL Philippe… - IEEE Transactions on …, 2006 - ieeexplore.ieee.org
Early performance feedback and design space exploration of complete field-programmable
gate array (FPGA) designs are still time consuming tasks. This paper proposes an original …