An area efficient network on chip architecture using high performance pipelines FIFO technique
S Sariga, C Nandagopal - 2017 IEEE International Conference …, 2017 - ieeexplore.ieee.org
Most correspondence movement in today's Network on Chips (NOC) depends on switch for
unstable memory based outlines. The NOC ought to be intended to effectively deal with the …
unstable memory based outlines. The NOC ought to be intended to effectively deal with the …
[PDF][PDF] Variable Latency Approach in VLSI Adder Implemented to Reduce Area and Power
K Kaarthik, C Vivek - Indian Journal …, 2018 - sciresol.s3.us-east-2.amazonaws …
Abstract Objective: The Ultimate aim of the VLSI Design is to improve the efficiency,
Reduction of Delay and Power Consumption and to minimize the area. In our proposed …
Reduction of Delay and Power Consumption and to minimize the area. In our proposed …
Tuberculosis malady recognition in chest radiographs via artificial neural networks
A Sridevi, GKDP Venkatesan - 2017 IEEE International …, 2017 - ieeexplore.ieee.org
This proposed method will give a suggestion for Tuberculosis (TB) diagnosing using
Artificial Neural Networks (ANN). Since diagnostic imaging techniques such as x-rays …
Artificial Neural Networks (ANN). Since diagnostic imaging techniques such as x-rays …
[PDF][PDF] WASHING MACHINE AUTOMATION USING FU Y LOGIC TECHNIQUE
K Kaarthik, A Sridevi - shanlax.com
Abstract The Fuzzy Logic Control technique can be a special type of control technique used
in various fields of Industry. It may consider the possible number of Parameters as Input to …
in various fields of Industry. It may consider the possible number of Parameters as Input to …
[引用][C] An Efficient Architecture Implemented to Reduce Area in VLSI Adders
K Kaarthik, S Pradeep, S Selvi - Imperial Journal of Interdisciplipary Research (IJIR), 2017