The origin and implications of dark matter anisotropic cosmic infall on ≈L haloes

D Aubert, C Pichon, S Colombi - Monthly Notices of the Royal …, 2004 - academic.oup.com
We measure the anisotropy of dark matter flows on small scales (∼ 500 kpc) in the near
environment of haloes using a large set of simulations. We rely on two different approaches …

[图书][B] Asynchronous circuit design

CJ Myers - 2001 - books.google.com
With asynchronous circuit design becoming a powerful tool in the development of new
digital systems, circuit designers are expected to have asynchronous design skills and be …

A methodology for correct-by-construction latency insensitive design

LP Carloni, KL McMillan, A Saldanha… - The Best of ICCAD: 20 …, 2003 - Springer
Abstract In Deep Sub-Micron (DSM) designs, performance will depend critically on the
latency of long wires. We propose a new synthesis methodology for synchronous systems …

[图书][B] Logically determined design: clockless system design with NULL convention logic

KM Fant - 2005 - books.google.com
This seminal book presents a new logically determined design methodology for designing
clockless circuit systems. The book presents the foundations, architectures and …

Click elements: An implementation style for data-driven compilation

A Peeters, F Te Beest, M De Wit… - 2010 IEEE Symposium …, 2010 - ieeexplore.ieee.org
This paper presents a new design template and design flow for the implementation of data-
driven asynchronous circuits. It relies on the use of edge-triggered flip-flops as the only …

Dual-hiding side-channel-attack resistant FPGA-based asynchronous-logic AES: Design, countermeasures and evaluation

KS Chong, JS Ng, J Chen, NKZ Lwin… - IEEE Journal on …, 2021 - ieeexplore.ieee.org
We present a side-channel-attack (SCA) resistant asynchronous-logic (async-logic)
Advanced Encryption Standard (AES) accelerator with dual-hiding SCA countermeasures, ie …

Delay insensitive system-on-chip interconnect using 1-of-4 data encoding

WJ Bainbridge, SB Furber - Proceedings Seventh International …, 2001 - ieeexplore.ieee.org
The demands of System-on-Chip (SoC) interconnect increasingly cannot be satisfied
through the use of a shared bus. A common alternative, using unidirectional, point-to-point …

Towards hazard-free multiplexer based implementation of self-timed circuits

A Kushnerov, M Medina… - 2021 27th IEEE …, 2021 - ieeexplore.ieee.org
The cost of design, test and fabrication of self-timed circuits remains prohibitive for their
wider adoption in practice. Addressing this issue, researchers are trying to find ways for …

An asynchronous instruction length decoder

KS Stevens, S Rotem, R Ginosar… - IEEE Journal of solid …, 2001 - ieeexplore.ieee.org
This paper describes an investigation of potential advantages and pitfalls of applying an
asynchronous design methodology to an advanced microprocessor architecture. A prototype …

The design of high-performance dynamic asynchronous pipelines: Lookahead style

M Singh, SM Nowick - IEEE Transactions on Very Large Scale …, 2007 - ieeexplore.ieee.org
A new class of asynchronous pipelines is proposed, called lookahead pipelines (LP), which
use dynamic logic and are capable of delivering multi-gigahertz throughputs. Since they are …