A machine learning approach for performance prediction and scheduling on heterogeneous CPUs

D Nemirovsky, T Arkose, N Markovic… - 2017 29th …, 2017 - ieeexplore.ieee.org
As heterogeneous systems become more ubiquitous, computer architects will need to
develop novel CPU scheduling techniques capable of exploiting the diversity of …

A scheduling method for multi-robot assembly of aircraft structures with soft task precedence constraints

V Tereshchuk, N Bykov, S Pedigo, S Devasia… - Robotics and Computer …, 2021 - Elsevier
The use of multiple cooperating robotic manipulators to assemble large aircraft structures
entails the scheduling of many discrete tasks such as drilling holes and installing fasteners …

Contention-aware fair scheduling for asymmetric single-ISA multicore systems

A Garcia-Garcia, JC Saez… - IEEE Transactions on …, 2018 - ieeexplore.ieee.org
Asymmetric single-ISA multicore processors (AMPs), which integrate high-performance big
cores and low-power small cores, were shown to deliver higher performance per watt than …

[PDF][PDF] Impact of Process Execution and Physical Memory-Spaces on OS Performance

HI Dino, S Zeebaree, AA Salih, RR Zebari… - … Reports of Kansai …, 2020 - researchgate.net
The importance of process monitoring applications continues to grow. Generally, many of
the developments in process monitoring are being driven by access to more and more data …

Flexible system software scheduling for asymmetric multicore systems with PMCSched: A case for Intel Alder Lake

C Bilbao, JC Saez… - … and Computation: Practice …, 2023 - Wiley Online Library
Asymmetric multicore processors (AMPs) couple high‐performance big cores and power‐
efficient small ones, all exposing a shared instruction set architecture to software, but with …

An intelligent task scheduling mechanism for autonomous vehicles via deep learning

G Balasekaran, S Jayakumar, R Pérez de Prado - Energies, 2021 - mdpi.com
With the rapid development of the Internet of Things (IoT) and artificial intelligence,
autonomous vehicles have received much attention in recent years. Safe driving is one of …

Evaluation of the intel thread director technology on an alder lake processor

JC Saez, M Prieto-Matias - Proceedings of the 13th ACM SIGOPS Asia …, 2022 - dl.acm.org
Asymmetric multicore processors (AMPs) combine high-performance big cores with more
energy-efficient small cores, all exposing a shared instruction-set architecture but different …

Appropriate allocation of workloads on performance asymmetric multicore architectures via deep learning algorithms

B Gomatheeshwari, J Selvakumar - Microprocessors and Microsystems, 2020 - Elsevier
Asymmetric multicore processors (AMP) have become popular in both high-end and low-
end computing systems due to its flexibility and high performance. A performance …

A Heterogeneity-Aware Replacement Policy for the Partitioned Cache on Asymmetric Multi-Core Architectures

J Fang, H Kong, H Yang, Y Xu, M Cai - Micromachines, 2022 - mdpi.com
In an asymmetric multi-core architecture, multiple heterogeneous cores share the last-level
cache (LLC). Due to the different memory access requirements among heterogeneous …

LFOC: A lightweight fairness-oriented cache clustering policy for commodity multicores

A Garcia-Garcia, JC Saez, F Castro… - Proceedings of the 48th …, 2019 - dl.acm.org
Multicore processors constitute the main architecture choice for modern computing systems
in different market segments. Despite their benefits, the contention that naturally appears …