Apparatus and methods are disclosed for adjusting phase of data signals to compensate for
phase-offset variations between devices during normal operation. The phase of data signals …

Methods and systems for calibrating a multi-mode, multi-standard transmitter and receiver
are disclosed. Aspects of the method may include configuring calibration paths in a …

US7363563B1 - Systems and methods for a built in test circuit for asynchronous testing of
high-speed transceivers - Google Patents US7363563B1 - Systems and methods for a built in …

(57) ABSTRACT A memory system includes a memory controller and a memory component
coupled to each other. The memory con troller includes an interface to receive a first signal …

A Circuit for reducing the number of serial ATA external PHY signals includes: a
serializer/deserializer, connected to a storage medium controller through a set of parallel …

See application file for complete search history. serializer/deserializer (SerDes) or other
transceivers. Mul tiple data paths in a finite impulse response (FIR) filter of transmitter of the …

Related US Application Data A Switch, Switched architecture and process for transferring
(60) Continuation of application No. 10/348,687, filed on data through an FCAL switch is …

A phase lock loop frequency synthesizer includes a phase rotator in the feedback path of the
PLL. The PLL includes a phase detector, a low pass filter, a charge pump, a voltage …

Testing a transceiver includes providing a sequence of test signals. A serialization clock is
generated and jitter is added to the clock in a knoWn and controlled manner. The test …

A memory component includes a memory core comprising dynamic random access memory
(DRAM) storage cells and a first circuit to receive external commands. The external …