Reliability-and process-variation aware design of integrated circuits
M Alam - Microelectronics Reliability, 2008 - Elsevier
We review the literature for reliability-and process-variation aware VLSI design to find that
an exciting area of research/application is rapidly emerging as a core topic of IC design …
an exciting area of research/application is rapidly emerging as a core topic of IC design …
High temperature gate-bias and reverse-bias tests on SiC MOSFETs
L Yang, A Castellazzi - Microelectronics Reliability, 2013 - Elsevier
As SiC MOSFET manufacturing technology continues to mature, an assessment of the
stability and reliability becomes essential for the advanced development of the devices …
stability and reliability becomes essential for the advanced development of the devices …
Cloud-based online ageing monitoring for IoT devices
GH Lian, WY Chen, SY Huang - IEEE Access, 2019 - ieeexplore.ieee.org
Reliability of an electronic device, concerning if it can function reliably over its designated
lifetime in the field (such as 10 or 15 years), has become more and more important in today's …
lifetime in the field (such as 10 or 15 years), has become more and more important in today's …
A computational model of NBTI and hot carrier injection time-exponents for MOSFET reliability
H Kufluoglu, MA Alam - Journal of Computational Electronics, 2004 - Springer
Theories of interface trap generation in Negative Bias Temperature Instability (NBTI) and Hot
Carrier Injection (HCI) mechanisms are unified under the geometric interpretation and …
Carrier Injection (HCI) mechanisms are unified under the geometric interpretation and …
Ultralow-power SRAM technology
RW Mann, WW Abadeer, MJ Breitwisch… - IBM Journal of …, 2003 - ieeexplore.ieee.org
An ultralow-standby-power technology has been developed in both 0.18-µm and 0.13-µm
lithography nodes for embedded and standalone SRAM applications. The ultralow-leakage …
lithography nodes for embedded and standalone SRAM applications. The ultralow-leakage …
Analysis of abnormal GIDL current degradation under hot carrier stress in DSOI-MOSFETs
It is generally believed that the gate-induced drain leakage (GIDL) current would increase
with the hot carrier stress (HCS) time. As more interface electron traps are generated near …
with the hot carrier stress (HCS) time. As more interface electron traps are generated near …
Reliability-and process-variation aware design of vlsi circuits
We review the literature for reliability-and process-variation aware VLSI design to find that
an exciting area of research/application is rapidly emerging as a core topic of IC design …
an exciting area of research/application is rapidly emerging as a core topic of IC design …
Impact of mechanical stress on the electrical performance of 3D NAND
We have developed a methodology for analyzing the impact of mechanical stress on the
electrical performance of 3D NAND devices. The methodology relies on in-situ electrical …
electrical performance of 3D NAND devices. The methodology relies on in-situ electrical …
MOSFET degradation due to negative bias temperature instability (NBTI) and hot carrier injection (HCI), and its implications for reliability-aware VLSI design
H Kufluoglu - 2007 - search.proquest.com
The scaling trends in CMOS technology and operating conditions give rise to serious
degradation mechanisms such as Negative Bias Temperature Instability (NBTI) and Hot …
degradation mechanisms such as Negative Bias Temperature Instability (NBTI) and Hot …
Modeling of Subsurface Leakage Current in Low Short Channel MOSFET at Accumulation Bias
We present a phenomenological model for subsurface leakage current in MOSFETs biased
in accumulation. The subsurface leakage current is mainly caused by source–drain …
in accumulation. The subsurface leakage current is mainly caused by source–drain …