Low-power SAR ADC design: Overview and survey of state-of-the-art techniques
This paper presents an overview for low-power successive approximation register (SAR)
analog-to-digital converters (ADCs). It covers the operation principle, error analysis, and …
analog-to-digital converters (ADCs). It covers the operation principle, error analysis, and …
A 12-b 18-GS/s RF sampling ADC with an integrated wideband track-and-hold amplifier and background calibration
AMA Ali, H Dinc, P Bhoraskar… - IEEE Journal of Solid …, 2020 - ieeexplore.ieee.org
We discuss a 12-b 18-GS/s analog-to-digital converter (ADC) implemented in 16-nm FinFET
process. The ADC is composed of an integrated high-speed track-and-hold amplifier (THA) …
process. The ADC is composed of an integrated high-speed track-and-hold amplifier (THA) …
A 12-b 10-GS/s interleaved pipeline ADC in 28-nm CMOS technology
S Devarajan, L Singer, D Kelly, T Pan… - IEEE Journal of Solid …, 2017 - ieeexplore.ieee.org
A 12-bit 10-GS/s interleaved (IL) pipeline analog-to-digital converter (ADC) is described in
this paper. The ADC achieves a signal to noise and distortion ratio (SNDR) of 55 dB and a …
this paper. The ADC achieves a signal to noise and distortion ratio (SNDR) of 55 dB and a …
Low voltage, low power, inverter-based switched-capacitor delta-sigma modulator
An operational transconductance amplifier (OTA) is a major building block and consumes
most of the power in switched-capacitor (SC) circuits, but it is difficult to design low-voltage …
most of the power in switched-capacitor (SC) circuits, but it is difficult to design low-voltage …
A 14 bit 1 GS/s RF sampling pipelined ADC with background calibration
AMA Ali, H Dinc, P Bhoraskar, C Dillon… - IEEE Journal of Solid …, 2014 - ieeexplore.ieee.org
We discuss a 14 bit 1 GS/s RF sampling pipelined ADC that utilizes correlation-based
background calibration to correct the inter-stage gain, settling and memory errors. To …
background calibration to correct the inter-stage gain, settling and memory errors. To …
Comparator-based switched-capacitor circuits for scaled CMOS technologies
JK Fiorenza, T Sepke, P Holloway… - IEEE Journal of Solid …, 2006 - ieeexplore.ieee.org
A comparator-based switched-capacitor circuit (CBSC) technique is presented for the design
of analog and mixed-signal circuits in scaled CMOS technologies. The technique involves …
of analog and mixed-signal circuits in scaled CMOS technologies. The technique involves …
A 16-bit, 125 ms/s, 385 mw, 78.7 db snr cmos pipeline adc
S Devarajan, L Singer, D Kelly, S Decker… - IEEE Journal of Solid …, 2009 - ieeexplore.ieee.org
A 16-bit 125 MS/s pipeline analog-to-digital converter (ADC) implemented in a 0.18¿ m
CMOS process is presented in this paper. A SHA-less 4-bit front-end is used to achieve low …
CMOS process is presented in this paper. A SHA-less 4-bit front-end is used to achieve low …
A 12 bit 160 MS/s two-step SAR ADC with background bit-weight calibration using a time-domain proximity detector
A 12 bit 160 MS/s two-step pipelined SAR ADC was fabricated in a 40 nm CMOS low-
leakage digital process. A background bit-weight calibration exploiting the comparator …
leakage digital process. A background bit-weight calibration exploiting the comparator …
A 12-bit 200-mhz cmos adc
A pipelined ADC incorporates a blind LMS calibration algorithm to correct for capacitor
mismatches, residue gain error, and op amp nonlinearity. The calibration applies 128 levels …
mismatches, residue gain error, and op amp nonlinearity. The calibration applies 128 levels …
A 16-bit 250-MS/s IF sampling pipelined ADC with background calibration
AMA Ali, A Morgan, C Dillon… - IEEE Journal of Solid …, 2010 - ieeexplore.ieee.org
This paper describes a 16-bit 250 MS/s ADC fabricated on a 0.18 BiCMOS process. The
ADC has an integrated input buffer with a new linearization technique that improves its …
ADC has an integrated input buffer with a new linearization technique that improves its …