Board-level functional fault identification using streaming data
High integration densities and design complexity of printed-circuit boards make board-level
functional fault identification extremely difficult. Machine learning provides an opportunity to …
functional fault identification extremely difficult. Machine learning provides an opportunity to …
Fine-grained adaptive testing based on quality prediction
The ever-increasing complexity of integrated circuits inevitably leads to high test cost.
Adaptive testing provides an effective solution for test-cost reduction; this testing framework …
Adaptive testing provides an effective solution for test-cost reduction; this testing framework …
Knowledge transfer in board-level functional fault diagnosis enabled by domain adaptation
High integration densities and design complexity make board-level functional fault diagnosis
extremely difficult. Machine-learning techniques can identify functional faults with high …
extremely difficult. Machine-learning techniques can identify functional faults with high …
Knowledge transfer in board-level functional fault identification using domain adaptation
High integration densities and design complexity make board-level functional fault
identification extremely difficult. Machine-learning techniques can identify functional faults …
identification extremely difficult. Machine-learning techniques can identify functional faults …
E-SCOUT: Efficient-Spatial Clustering-based Outlier Detection through Telemetry
Silicon lifecycle management (SLM) is needed to ensure silicon-product reliability and
quality. Prior methods utilize off-chip solutions to identify malware, diagnose bugs, and …
quality. Prior methods utilize off-chip solutions to identify malware, diagnose bugs, and …
Access-time minimization for the IJTAG network using data broadcast and hardware parallelism
Z Zhong, G Li, Q Yang… - IEEE Transactions on …, 2020 - ieeexplore.ieee.org
The IEEE Std. 1687 facilitates flexible access to on-chip instruments through the JTAG test-
access port. This flexibility enables the minimization of the overall access time (OAT), and a …
access port. This flexibility enables the minimization of the overall access time (OAT), and a …
Access-time minimization in the IEEE 1687 network using broadcast and hardware parallelism
Z Zhong, G Li, Q Yang… - 2018 IEEE International …, 2018 - ieeexplore.ieee.org
The IEEE Std. 1687 facilitates flexible access to on-chip instruments through the JTAG test-
access port. This flexibility enables the minimization of the overall access time (OAT), and a …
access port. This flexibility enables the minimization of the overall access time (OAT), and a …
Machine Learning Support for Board-Level Functional Fault Diagnosis
The ever-increasing integration density and design complexity of printed-circuit boards are
making functional fault diagnosis extremely challenging. The cost associated with the …
making functional fault diagnosis extremely challenging. The cost associated with the …
Test-cost reduction for 2.5 D ICs using microspring technology for die attachment and rework
Interposer-based 2.5 D integrated circuits (ICs) are being increasingly adopted in the
semiconductor industry for FPGAs and GPUs. However, the cost of testing is still a major …
semiconductor industry for FPGAs and GPUs. However, the cost of testing is still a major …
Adaptive Methods for Machine Learning-Based Testing of Integrated Circuits and Boards
M Liu - 2020 - search.proquest.com
The relentless growth in information technology and artificial intelligence (AI) is placing
demands on integrated circuits and boards for high performance, added functionality, and …
demands on integrated circuits and boards for high performance, added functionality, and …