Effects of metal work function and gate-oxide dielectric on super high frequency performance of a non-align junction DG-MOSFET based inverter in the sub-100 nm …
This paper presents simulation analysis of an inverter made from non-aligned double gate
field effect transistors (NADGFETs) in Sub-100 nm regime. The inverter consists of n …
field effect transistors (NADGFETs) in Sub-100 nm regime. The inverter consists of n …
A simulation study of SiGe shell channel CFET for sub-2-nm technology nodes
X Shi, T Liu, Y Wang, R Chen, N Zhang… - … on Electron Devices, 2023 - ieeexplore.ieee.org
In this article, a SiGe shell complementary FET (CFET) composed of an inversion mode (IM)
nFET and a junctionless accumulation mode pFET under 2-nm (N2) and 1.5-nm (N1. 5) …
nFET and a junctionless accumulation mode pFET under 2-nm (N2) and 1.5-nm (N1. 5) …
[PDF][PDF] Work-function tuning on analogue properties of junction-less strained DG-MOSFET
KE Kaharudin, F Salehuddin… - Journal of Engineering …, 2023 - researchgate.net
This paper discusses an extensive investigation on the influence of work-function (WF)
tuning on analogue properties of the n-type junction-less strained doublegate MOSFET. The …
tuning on analogue properties of the n-type junction-less strained doublegate MOSFET. The …
Taper-Angle-Induced Variation in n/p-Stacked Versus p/n-Stacked CFET
E Jang, M Kim, C Shin - IEEE Transactions on Electron Devices, 2024 - ieeexplore.ieee.org
The complementary field-effect transistor (CFET), comprising vertically stacked gate-all-
around field-effect transistor (GAAFETs), is a promising candidate to significantly enhance …
around field-effect transistor (GAAFETs), is a promising candidate to significantly enhance …
Simulation study of lateral CEFT logic performance at 3 nm Node
G Wen, Q Long, X Shi, Y Wang, F Liu, H Hu… - Microelectronics …, 2023 - Elsevier
In this paper, a lateral CFET comprising of n-type junctionless accumulation mode gate-all-
around (JAMGAA) Si-nanowire and p-channel inversion-mode gate-all-around (IMGAA) Si …
around (JAMGAA) Si-nanowire and p-channel inversion-mode gate-all-around (IMGAA) Si …
Complementary FET-The Future of the Semiconductor Transistor
SH Kim, SH Lee, WJ Lee, JW Park… - Electronics and …, 2023 - koreascience.kr
With semiconductor scaling approaching the physical limits, devices including CMOS
(complementary metal-oxide-semiconductor) components have managed to overcome yet …
(complementary metal-oxide-semiconductor) components have managed to overcome yet …
[图书][B] Design of Ultra-Compact and Low-Power sub-10 Nanometer Logic Circuits with Schottky Barrier Contacts and Gate Work-Function Engineering
TF Canan - 2022 - search.proquest.com
Abstract As modern Complementary Semiconductor Metal Oxide (CMOS) technology is
approaching to the end of scaling limits projected by Moore's Law, researchers are in a …
approaching to the end of scaling limits projected by Moore's Law, researchers are in a …