Substrate noise coupling in SoC design: Modeling, avoidance, and validation

A Afzali-Kusha, M Nagata, NK Verghese… - Proceedings of the …, 2006 - ieeexplore.ieee.org
Issues related to substrate noise in system-on-chip design are described including the
physical phenomena responsible for its creation, coupling transmission mechanisms and …

Modeling substrate effects in the design of high-speed Si-bipolar ICs

M Pfost, HM Rein, T Holzwarth - IEEE Journal of Solid-State …, 1996 - ieeexplore.ieee.org
In the design of high-speed IC's, the influence of the substrate on circuit performance must
be considered carefully. Therefore, in this paper the contribution of the p/sup-/substrate and …

Modeling and measurement of substrate coupling in Si-bipolar IC's up to 40 GHz

M Pfost, HM Rein - IEEE Journal of Solid-State Circuits, 1998 - ieeexplore.ieee.org
Parasitic substrate coupling can severely degrade the performance of high-speed ICs and
must be considered carefully in circuit design. Therefore, this paper proposes several …

Substrate coupling in digital circuits in mixed-signal smart-power systems

RM Secareanu, S Warner, S Seabridge… - … Transactions on Very …, 2004 - ieeexplore.ieee.org
This paper describes theoretical and experimental data characterizing the sensitivity of
nMOS and CMOS digital circuits to substrate coupling in mixed-signal, smart-power systems …

Challenges for signal integrity prediction in the next decade

X Aragones, A Rubio - Materials Science in Semiconductor Processing, 2003 - Elsevier
Noise caused by the activity of integrated circuits is a limiting factor for the development of
future VLSI circuits. Transients of voltages and currents couple perturbations to the co …

Characterization of crosstalk noise in submicron CMOS integrated circuits: An experimental view

JY Fourniols, M Roca, F Caignet… - IEEE transactions on …, 1998 - ieeexplore.ieee.org
A way to characterize the crosstalk noise susceptibility for integrated circuits fabrication
technologies is presented. A comparison between 0.7-and 0.35-/spl mu/m technologies …

Placement of substrate contacts to minimize substrate noise in mixed-signal integrated circuits

RM Secareanu, S Warner, S Seabridge… - … Integrated Circuits and …, 2001 - Springer
The placement of substrate contacts in epi and non-epi technologies is analyzed in order to
control and reduce the substrate noise amplitude and spreading. The choice of small or …

Differential sensing strategy for dynamic thermal testing of ICs

J Altet, A Rubio - … . 15th IEEE VLSI Test Symposium (Cat. No …, 1997 - ieeexplore.ieee.org
A new testing alternative based on thermal wave propagation is proposed. Some failures,
when activated, produce an increase in local power dissipation at various points. A thermal …

Parasitic modeling and noise mitigation in advanced RF/mixed-signal silicon germanium processes

R Singh, YV Tretiakov, JB Johnson… - … on Electron Devices, 2003 - ieeexplore.ieee.org
The potential for highly integrated radio frequency (RF) and mixed-signal (AMS) designs is
today very real with the availability cost-effective scaled silicon-germanium (SiGe) process …

Physical design to improve the noise immunity of digital circuits in a mixed-signal smart-power system

RM Secareanu, S Warner, S Seabridge… - … on Circuits and …, 2000 - ieeexplore.ieee.org
Theoretical, simulation and experimental analysis and data are presented, discussing
physical design techniques which influence the noise behavior of digital circuits in a mixed …