Cu annealing for improved data retention in flash memory devices

L You, A Nickel, MQ Tran, MV Ngo, H Pham… - US Patent …, 2011 - Google Patents
Data retention in flash memory devices, such as mirrorbit devices, is improved by reducing
the generation and/or diffusion of hydrogen ions during back end processing, such as …

Interconnect structure having enhanced electromigration reliability and a method of fabricating same

CC Yang, PC Wang, YY Wang - US Patent 7,569,475, 2009 - Google Patents
An interconnect structure having improved electromigration (EM) reliability is provided. The
inventive interconnect structure avoids a circuit dead opening that is caused by EM failure by …

Formation of aligned capped metal lines and interconnections in multilevel semiconductor structures

SR Chiras, MW Lane, SG Malhotra… - US Patent …, 2010 - Google Patents
In integrated circuit technology; an electromigration and diffusion sensitive conductor of a
metal such as copper and processing procedure therefore is provided, wherein, at a …

Method of forming an insulating capping layer for a copper metallization layer by using a silane reaction

J Hohage, M Lehr, V Kahlert - US Patent 7,678,699, 2010 - Google Patents
A new technique is disclosed in which a barrier/capping layer for a copper-based metal line
is formed by using a thermal-chemical treatment with a surface modification on the basis of a …

Organic insulating film, manufacturing method thereof, semiconductor device using such organic insulating film and manufacturing method thereof

K Ohto, T Usami, N Morita, K Endo - US Patent 7,763,979, 2010 - Google Patents
The dielectric constants of SiC and SiCN that are currently the subjects of much investigation
are both 4.5 to 5 or so and that of SiOC, 2.8 to 3.0 or so. With further miniaturization of the …

Semiconductor devices including silicide regions and methods of fabricating the same

S Kang, KS Park, B Lee, S Kang… - US Patent App. 14 …, 2015 - Google Patents
A semiconductor device has a silicide source/drain region is fabricated by growing silicon on
an epitaxial region including silicon and either germanium or carbon. In the method, a gate …

Method of forming an interconnect including a dielectric cap having a tensile stress

CC Yang, K Chanda, LA Clevenger, YY Wang… - US Patent …, 2009 - Google Patents
An interconnect structure and method of making the same are provided. The interconnect
structure includes a dielectric layer having a patterned opening, a metal feature disposed in …

Interconnect structure having enhanced electromigration reliability and a method of fabricating same

CC Yang, PC Wang, YY Wang - US Patent 8,138,083, 2012 - Google Patents
An interconnect structure having improved electromigration (EM) reliability is provided. The
inventive interconnect structure avoids a circuit dead opening that is caused by EM failure by …

Methods for improving uniformity of cap layers

CH Yu, MS Yeh, CH Lin, YC Lu, HL Chang - US Patent 8,987,085, 2015 - Google Patents
A method of forming an integrated circuit includes providing a semiconductor substrate,
forming a metallization layer over the semiconductor substrate, wherein the metallization …

Shallow trench isolation structure with low trench parasitic capacitance

VP Gopinath, A Kamath, MR Mirabedini… - US Patent …, 2009 - Google Patents
Provided are methods and composition for forming an isolation structure on an integrated
circuit substrate. First, a trench is etched in the integrated circuit substrate. A lower dielectric …