Practical algorithms for performance guarantees in buffered crossbars
This paper is about high capacity switches and routers that give guaranteed throughput, rate
and delay guarantees. Many routers are built using input queueing or combined input and …
and delay guarantees. Many routers are built using input queueing or combined input and …
CBF: A high-performance scheduling algorithm for buffered crossbar switches
Buffered crossbar switches have been considered as a viable alternative to bufferless
crossbar switches to improve the switching performance. An architecture that combines the …
crossbar switches to improve the switching performance. An architecture that combines the …
CIXOB-k: Combined input-crosspoint-output buffered packet switch
We propose a novel architecture, a combined input-crosspoint-output buffered (CIXOB-k,
where k is the size of the crosspoint buffer) Switch. CIXOB-k architecture provides 100 …
where k is the size of the crosspoint buffer) Switch. CIXOB-k architecture provides 100 …
On scheduling optical packet switches with reconfiguration delay
X Li, M Hamdi - IEEE Journal on Selected Areas in …, 2003 - ieeexplore.ieee.org
Using optical technology for the design of packet switches/routers offers several advantages
such as scalability, high bandwidth, power consumption, and cost. However, reconfiguring …
such as scalability, high bandwidth, power consumption, and cost. However, reconfiguring …
An evolution to crossbar switches with virtual output queuing and buffered cross points
K Yoshigoe, KJ Christensen - IEEE network, 2003 - ieeexplore.ieee.org
Input queued (IQ) switch architectures with virtual output queues (VOQ) scale up to very high
speeds and have been a subject of intense research in the past decade. VOQ IQ switches …
speeds and have been a subject of intense research in the past decade. VOQ IQ switches …
Output-queued switch emulation by fabrics with limited memory
RB Magill, CE Rohrs… - IEEE Journal on Selected …, 2003 - ieeexplore.ieee.org
The output-queued (OQ) switch is often considered an ideal packet switching architecture for
providing quality-of-service guarantees. Unfortunately, the high-speed memory …
providing quality-of-service guarantees. Unfortunately, the high-speed memory …
[PDF][PDF] Error Sensitivity of the Linux Kernel Executing on PowerPC G4 and Pentium 4 Processors.
W Gu, Z Kalbarczyk, RK Iyer - DSN, 2004 - researchgate.net
The goals of this study are:(i) to compare Linux kernel (2.4. 22) behavior under a broad
range of errors on two target processors—the Intel Pentium 4 (P4) running RedHat Linux 9.0 …
range of errors on two target processors—the Intel Pentium 4 (P4) running RedHat Linux 9.0 …
On the combined input-crosspoint buffered switch with round-robin arbitration
Input-buffered switches have been widely considered for implementing feasible packet
switches. However, their matching process may not be time-efficient for switches with high …
switches. However, their matching process may not be time-efficient for switches with high …
[图书][B] Interconnections for Computer Communications and Packet Networks
R Rojas-Cessa - 2016 - taylorfrancis.com
This book introduces different interconnection networks applied to different systems.
Interconnection networks are used to communicate processing units in a multi-processor …
Interconnection networks are used to communicate processing units in a multi-processor …
An efficient scheduling algorithm for combined input-crosspoint-queued (CICQ) switches
X Zhang, LN Bhuyan - IEEE Global Telecommunications …, 2004 - ieeexplore.ieee.org
With today's ASIC technology, a large amount of memory can be easily implemented in a
single chip. This makes the combined input-crosspoint-queued (CICQ) crossbar switch a …
single chip. This makes the combined input-crosspoint-queued (CICQ) crossbar switch a …