[图书][B] Comprehensive functional verification: The complete industry cycle

B Wile, J Goss, W Roesner - 2005 - books.google.com
One of the biggest challenges in chip and system design is determining whether the
hardware works correctly. That is the job of functional verification engineers and they are the …

Measuring program similarity: Experiments with SPEC CPU benchmark suites

A Phansalkar, A Joshi, L Eeckhout… - … Analysis of Systems …, 2005 - ieeexplore.ieee.org
It is essential that a subset of benchmark programs used to evaluate an architectural
enhancement, is well distributed within the target workload space rather than clustered in …

Measuring benchmark similarity using inherent program characteristics

A Joshi, A Phansalkar, L Eeckhout… - IEEE Transactions on …, 2006 - ieeexplore.ieee.org
This paper proposes a methodology for measuring the similarity between programs based
on their inherent microarchitecture-independent characteristics, and demonstrates two …

Control flow modeling in statistical simulation for accurate and efficient processor design studies

L Eeckhout, RH Bell Jr, B Stougie… - ACM SIGARCH …, 2004 - dl.acm.org
Designing a new microprocessor is extremely time-consuming. One of the contributing
reasons is that computerdesigners rely heavily on detailed architectural simulations, which …

Automated design of application specific superscalar processors: an analytical approach

TS Karkhanis, JE Smith - Proceedings of the 34th annual international …, 2007 - dl.acm.org
Analytical modeling is applied to the automated design of application-specific superscalar
processors. Using an analytical method bridges the gap between the size of the design …

Uncovering the performance bottleneck of modern HPC processor with static code analyzer: a case study on Kunpeng 920

S Tan, Q Jiang, Z Cao, X Hao, J Chen, H An - CCF Transactions on High …, 2024 - Springer
The performance of high-performance computing (HPC) and other real-world applications is
becoming unpredictable as the micro-architecture of the modern central processing unit …

Minimizing memory requirements in rate-optimal schedules

R Govindarajan, GR Gao… - Proceedings of IEEE …, 1994 - ieeexplore.ieee.org
We address the problem of minimizing buffer storage requirement in constructing rate-
optimal compile-time schedules for multi-rate dataflow graphs. We demonstrate that this …

Memory data flow modeling in statistical simulation for the efficient exploration of microprocessor design spaces

D Genbrugge, L Eeckhout - IEEE Transactions on Computers, 2007 - ieeexplore.ieee.org
Microprocessor design is both complex and time consuming: exploring a huge design space
for identifying the optimal design under a number of constraints is infeasible using detailed …

Architecting graphics processors for non-graphics compute acceleration

TM Aamodt - 2009 IEEE Pacific Rim Conference on …, 2009 - ieeexplore.ieee.org
This paper discusses the emergence of graphics processing units (GPUs) that contain
architecture features for accelerating non-graphics (or GPGPU) applications. It provides an …

The simcore/alpha functional simulator

K Kise, T Katagiri, H Honda, T Yuba - … of the 2004 workshop on computer …, 2004 - dl.acm.org
We have developed a function-level processor simulator, SimCore/Alpha Functional
Simulator Version 2.0 (SimCore Version 2.0), for processor architecture research and …