A novel fault-tolerant logic style with self-checking capability
We introduce a novel logic style with self-checking capability to enhance hardware reliability
at logic level. The proposed logic cells have two-rail inputs/outputs, and the functionality for …
at logic level. The proposed logic cells have two-rail inputs/outputs, and the functionality for …
A fault-resistant architecture for aes s-box architecture
This paper introduces a high-Speed fault-resistant hardware implementation for the S-box of
AES cryptographic algorithm, called HFS-box. A deep pipelining for S-box at the gate level is …
AES cryptographic algorithm, called HFS-box. A deep pipelining for S-box at the gate level is …