Study and analysis of advanced 3D multi-gate junctionless transistors
As the IC technology is evolving very rapidly, the feature size of the device has been
migrating to sub-nanometre regime for achieving the high packing density. To continue with …
migrating to sub-nanometre regime for achieving the high packing density. To continue with …
Enhancing the delay performance of junctionless silicon nanotube based 6T SRAM
This work investigates the delay performance of junctionless silicon nanotube (JLSiNT) field‐
effect transistor (FET) based 6T SRAM cell. The study demonstrates that the delay …
effect transistor (FET) based 6T SRAM cell. The study demonstrates that the delay …
Sensitivity of silicon nanotube field effect transistor to structural process parameters
R Ambika, R Srinivasan - Journal of Nanoelectronics and …, 2017 - ingentaconnect.com
In this paper, we have studied the impact of various geometrical parameters on the
performance of Silicon Nanotube Field Effect Transistor (SiNT-FET) using 3D numerical …
performance of Silicon Nanotube Field Effect Transistor (SiNT-FET) using 3D numerical …
RF Analysis of Silicon Nanotube FET for Ultra-Low-Power Applications
A Josephine Anucia, D Jackuline Moni… - Advances in Automation …, 2021 - Springer
Abstracts The device performance of 3D vertical silicon nanotube FET is discussed. The
short channel effect is controlled by inner and outer gates in the device which affords the …
short channel effect is controlled by inner and outer gates in the device which affords the …
Investigation of independent gate operation in junctionless silicon nanotube FET using 3D numerical simulations
R Ambika, R Srinivasan - 2017 International Conference on …, 2017 - ieeexplore.ieee.org
In this paper, we investigate the independent gate operation in Junction-less Silicon
Nanotube FET (JLSiNT-FET) device using TCAD 3D simulations. JLSiNT-FET has two gates …
Nanotube FET (JLSiNT-FET) device using TCAD 3D simulations. JLSiNT-FET has two gates …