Low power multiplier architectures using Vedic mathematics in 45nm technology for high speed computing
Speed and the overall performance of any digital signal processor are largely determined by
the efficiency of the multiplier units present within. The use of Vedic mathematics has …
the efficiency of the multiplier units present within. The use of Vedic mathematics has …
[PDF][PDF] A Comparative Analysis of Multiplier Topologies using Different Vedic Sutras
K Mounika, AD Reddy - International Journal of Engineering Research & …, 2012 - ijatir.org
The need of low area and high speed Multiplier is increasing as the need of high speed
processors are needed. The multipliers used in Square and cube architecture have to be …
processors are needed. The multipliers used in Square and cube architecture have to be …
[PDF][PDF] Low Power Multiplier Architectures using Vedic Mathematics in 45nm Technology for High Speed Devices
K MOUNIKA, AD REDDY - 2016 - ijatir.org
The need of low area and high speed Multiplier is increasing as the need of high speed
processors are needed. The multipliers used in Square and cube architecture have to be …
processors are needed. The multipliers used in Square and cube architecture have to be …
[PDF][PDF] High Speed Implementation of 16 x 16 Multiplier Using Vedic Mathematics–A Review
S Sharan, PM Gulhane - 2012 - ijaece.com
Extremely economical arithmetic operations are necessary to understand the required
performance in many periods of time systems and digital image methodology applications …
performance in many periods of time systems and digital image methodology applications …
[引用][C] Low Power Multiplier Architectures Using Vedic Mathematics in 45nm Technology for High Speed Computing
M Lavanya, M Tech, NS Kumar