This paper introduces a ΔΣ fractional-N digital PLL based on a single-bit TDC. A digital-to-
time converter, placed in the feedback path, cancels out the quantization noise introduced …

A digital PLL (DPLL) with a time-to-digital converter (TDC) embedded within a digitally
controlled oscillator (DCO) has been implemented in 65 nm CMOS occupying an active area …

In digital bang-bang phase-locked loops (BBPLLs), both the hard nonlinearity of the phase
detector and the frequency granularity of the digitally controlled oscillator (DCO) can give …

This paper presents an all-digital phase-locked loop (AD-PLL) using a voltage-domain
digitization realized by an analog-to-digital converter (ADC) instead of adopting a traditional …

This work introduces an accurate linearized model and phase noise spectral analysis of
digital bang-bang PLLs, that includes both the reference and the digitally-controlled …

As digital CMOS technology scales to 32nm and below, small and low-voltage clock and
timing generators are in high demand to avoid complex analog operations and to meet …

An all-digital phase-locked loop with a bang-bang phase-frequency detector (BBPFD) that
tracks the optimum loop gain for minimum jitter is proposed. The autocorrelation of the …

This paper presents a digital bang-bang phase-locked loop (DBPLL) that employs automatic
loop gain control and loop latency reduction techniques to enhance the jitter performance …

State of the art digital PLLs can be divided in two categories, depending on the
implementation of the digital phase detector. Digital clocking and wireline applications …

We present a linearized analysis of bang-bang phase-locked loops (PLLs) in the frequency
domain that is complete and self-consistent. It enables the manual design of frequency …