Ultra-thin body & buried oxide SOI substrate development and qualification for fully depleted SOI device with back bias capability

W Schwarzenbach, BY Nguyen, F Allibert, C Girard… - Solid-State …, 2016 - Elsevier
This paper reviews the properties of the SOI wafers fabricated using the Smart Cut™
technology, with ultra-thin body and buried oxide (BOX) required for the FD-SOI CMOS …

Fabrication and characterization of silicon-on-insulator wafers

T Kim, J Lee - Micro and Nano Systems Letters, 2023 - Springer
Abstract Silicon-on-insulator (SOI) wafers offer significant advantages for both Integrated
circuits (ICs) and microelectromechanical systems (MEMS) devices with their buried oxide …

Planar fully-depleted-silicon-on-insulator technologies: Toward the 28 nm node and beyond

B Doris, B DeSalvo, K Cheng, P Morin, M Vinet - Solid-State Electronics, 2016 - Elsevier
This paper presents a comprehensive overview of the research done in the last decade on
planar Fully-Depleted-Silicon-On-Insulator (FDSOI) technologies in the frame of the joint …

SOI-type bonded structures for advanced technology nodes

J Widiez, JM Hartmann, F Mazen, S Sollier… - ECS …, 2014 - iopscience.iop.org
Bulk silicon device technologies are reaching fundamental scaling limitations. The 28 nm
and 22 nm technology nodes have seen the introduction of Ultra-Thin Body and Buried …

Engineered substrates for Moore and more than Moore's law: Device scaling: Entering the substrate era

C Maleville - 2015 IEEE SOI-3D-Subthreshold Microelectronics …, 2015 - ieeexplore.ieee.org
Since 10 years, end markets drastically changed towards mobile connected users and
typical performance/cost KPIs have evolved towards more demanding PPAC (Power …

Refractive index sensing using silicon-on-insulator waveguide based directional coupler

R Dwivedi, A Kumar - IEEE sensors letters, 2018 - ieeexplore.ieee.org
We propose a refractive index (RI) sensor based on a vertical directional coupling between
two silicon-on-insulator (SOI) waveguides. It is shown that by optimizing the SOI waveguide …

Down to 15nm BOX: SOI extendability for planar fully depleted application beyond 22FD

W Schwarzenbach, F Allibert… - 2016 IEEE SOI-3D …, 2016 - ieeexplore.ieee.org
SOI wafers have been used for digital applications for 2 decades. Historically separated
between the high-performance, Partially Depleted (PDSOI)[1] and ultra-low power Fully …

Systematic evaluation of SOI buried oxide reliability for partially depleted and fully depleted applications

W Schwarzenbach, C Malaquin… - 2015 IEEE SOI-3D …, 2015 - ieeexplore.ieee.org
SOI Buried Oxide (BOX) electrical quality is assessed through Charge to Breakdown,
Breakdown Voltage, low field leakage, BOX fixed charge density and BOX/Si interface trap …

Double SOI substrates for advanced technologies

W Schwarzenbach, G Besnard… - 2019 IEEE SOI-3D …, 2019 - ieeexplore.ieee.org
Beyond conventional FinFet & FD-SOI device architectures, Complementary FET (CFET) is
considered. To support this 3D approach, improving integration, manufacturing and paving …

Engineered substrates for advanced CMOS technology nodes and More-than-Moore applications

KK Bourdelle - Functional Nanomaterials and Devices for Electronics …, 2014 - Springer
Traditional planar bulk or partially depleted SOI (PDSOI) CMOS transistor architectures at
present leading edge of miniaturization are plagued by limitations due to unacceptably high …