This paper proposes a coarse-grained dynamically reconfigurable architecture that offers
flexible reliability to deal with soft errors and aging. The notion of a cluster is introduced as a …

Hardware redundancy is a common method for improving the reliability of a system. The
disadvantage of this approach is the hardware overhead and the additional power …

This paper presents the implementation of the error recovery scheme from temporary faults,
applicable for datapaths of coarse-grained reconfigurable architectures. We have chosen …

In this contribution we apply a novel strategy for partial remapping to significantly enhance
the reliability of coarse-grained reconfigurable architectures. If a component of the …

This paper presents the implementation of the coarse-grained reconfigurable architecture
(CGRA) DART with on-line error detection intended for increasing fault-tolerance. Most parts …

The ever growing demands of embedded systems to satisfy high computing performance
and cost efficiency lead to the trend of using commercial off-the-shelf hardware. However …

Triple modular redundancy (TMR) is a common method to implement fault-tolerant circuits.
Traditionally, TMR is realized by triplication of components. In order to reduce the area …

Presents a comparison of superscalar and decoupled access/execute architectures. Both
architectures attempt to exploit instruction-level parallelism by issuing multiple instructions …

In this paper, we propose a polymorphic fault tolerant architecture that can be tailored to
efficiently support the reliability needs of multiple applications at run-time. Today, coarse …

This paper presents a mixed-grained reconfigurable VLSI array architecture that can cover
mission-critical applications to consumer products through C-to-array application mapping …