A critical review on performance, reliability, and fabrication challenges in nanosheet FET for future analog/digital IC applications

S Valasa, S Tayal, LR Thoutam, J Ajayan… - Micro and …, 2022 - Elsevier
This article critically reviews the fabrication challenges, emerging materials (wafer, high-k
oxide, gate metal, channel materials), dimensional influences, thermal effects, growth …

Design and investigation of a novel gate-all-around vertical tunnel FET with improved DC and analog/RF parameters

KRN Karthik, CK Pandey - ECS Journal of Solid State Science …, 2022 - iopscience.iop.org
In this paper, a novel structure of gate-all-around vertical TFET (GAA-VTFET) is proposed
and investigated for the first time with the help of 3D TCAD simulator. It is found that GAA …

Improvement in self-heating characteristic by incorporating hetero-gate-dielectric in gate-all-around MOSFETs

YS Song, JH Kim, G Kim, HM Kim… - IEEE Journal of the …, 2020 - ieeexplore.ieee.org
For improving self-heating effects (SHEs) in gate-all-around metal-oxide-semiconductor field-
effect transistors (GAA MOSFETs), hetero-gate-dielectric (HGD) is utilized. The HGD consists …

An intensive study of tree-shaped JL-NSFET: digital and analog/RF perspective

S Valasa, S Tayal, LR Thoutam - IEEE Transactions on Electron …, 2022 - ieeexplore.ieee.org
This manuscript for the first time presents the digital and analog/RF performance analysis for
novel Tree-shaped Junctionless Nanosheet (NS) FET. An additional inter-bridge (IB) …

Performance analysis of metal gate engineered junctionless nanosheet fet with a ft/fmax of 224/342ghz for beyond 5g (b5g) applications

S Valasa, S Tayal, LR Thoutam - Micro and Nanostructures, 2023 - Elsevier
This manuscript for the first time investigates the effect of Dual Metal on Gate Junctionless
Nanosheet FET (DMG-JL-NSFET) for analog/RF applications. The entire analysis is …

Reliable high-voltage drain-extended FinFET with thermoelectric improvement

KY Kim, YS Song, G Kim, S Kim… - IEEE Transactions on …, 2022 - ieeexplore.ieee.org
In this article, a reliable drain-extended (De) fin-shaped field-effect transistor (DeFinFET)
with improved thermal performance and electrical performance is proposed for high-voltage …

Nanowire transistors: a next step for the low-power digital technology

D Ajitha, K Vijaya Lakshmi… - IETE Journal of …, 2023 - Taylor & Francis
As conventional Complementary Metal Oxide Semiconductor (CMOS) reaches extreme
limitation to implement the digital circuits with high density and low power dissipation …

Improvement of self-heating effect in Ge vertically stacked GAA nanowire pMOSFET by utilizing Al2O3 for high-performance logic device and electrical/thermal co …

YS Song, S Kim, G Kim, H Kim, JH Lee… - Japanese Journal of …, 2021 - iopscience.iop.org
For improving self-heating effect (SHE) in Ge vertically stacked gate-all-around (GAA)
nanowire (NW) p-type metal-oxide-semiconductor field-effect transistor (pMOSFET) …

Design techniques for high reliability FET by incorporating new materials and electrical/thermal co-optimization

YS Song, SB Rahi, S Tayal, A Upadhyay… - Emerging Materials …, 2022 - Springer
This chapter addresses overall CMOS design techniques for the future technology nodes
(especially, sub 7-nm node technology). In the introduction, the emerging new materials and …

Optimizing device dimensions for dual material junctionless tree-FET: a path to improved analog/RF performance

D Beebireddy, K Fatima - ECS Journal of Solid State Science …, 2024 - iopscience.iop.org
This comprehensive study delves into the intricate analysis of the electrical and analog/RF
performance of the Dual Material (DM) junctionless (JL) Tree-FET. During the optimization …