BSIM: Berkeley short-channel IGFET model for MOS transistors

BJ Sheu, DL Scharfetter, PK Ko… - IEEE Journal of Solid …, 1987 - ieeexplore.ieee.org
The Berkeley short-channel IGFET model (BSIM), an accurate and computationally efficient
MOS transistor model, and its associated characterization facility for advanced integrated …

[图书][B] Mosfet modeling for VLSI simulation: theory and practice

N Arora - 2007 - books.google.com
A reprint of the classic text, this book popularized compact modeling of electronic and
semiconductor devices and components for college and graduate-school classrooms, and …

A quad CMOS single-supply op amp with rail-to-rail output swing

DM Monticelli - IEEE Journal of Solid-State Circuits, 1986 - ieeexplore.ieee.org
The realization of a commercially viable, general-purpose quad CMOS amplifier is
presented, along with discussions of the tradeoffs involved in such a design. The amplifier …

[PDF][PDF] Micropower techniques

EA Vittoz - Design of VLSI circuits for telecommunication and …, 1994 - researchgate.net
Micropower integrated circuits techniques and technologies were originally developed for
applications in electronic watches [1, 2]. Modern watch circuits have a complexity ranging …

Statistical analysis of subthreshold leakage current for VLSI circuits

R Rao, A Srivastava, D Blaauw… - IEEE Transactions on …, 2004 - ieeexplore.ieee.org
We develop a method to estimate the variation of leakage current due to both intra-die and
inter-die gate length process variability. We derive an analytical expression to estimate the …

A parametric short-channel MOS transistor model for subthreshold and strong inversion current

T Grotjohn, B Hoefflinger - IEEE journal of solid-state circuits, 1984 - ieeexplore.ieee.org
The authors present a parametric model which covers the subthreshold and strong inversion
regions with a continuous transition between these regions. The effects included in the …

Duet: An accurate leakage estimation and optimization tool for dual-V/sub t/circuits

S Sirichotiyakul, T Edwards, C Oh… - … Transactions on Very …, 2002 - ieeexplore.ieee.org
Presents a new approach for the estimation and optimization of standby power dissipation in
large MOS digital circuits. We introduce a new approach for accurate and efficient …

Drain-induced barrier-lowering analysis in VSLI MOSFET devices using two-dimensional numerical simulations

SG Chamberlain, S Ramanan - IEEE transactions on electron …, 1986 - ieeexplore.ieee.org
In recent publications the drain-induced barrier-lowering (DIBL) effect has been included in
the determination of the drain current of short-channel MOSFET's by way of analytical …

[HTML][HTML] SRAM cell leakage control techniques for ultra low power application: a survey

P Bikki, P Karuppanan - Circuits and systems, 2017 - scirp.org
Low power supply operation with leakage power reduction is the prime concern in modern
nano-scale CMOS memory devices. In the present scenario, low leakage memory …

New simple procedure to determine the threshold voltage of MOSFETs

FJG Sánchez, A Ortiz-Conde, G De Mercato… - Solid-State …, 2000 - Elsevier
A new alternative technique is proposed to extract the threshold voltage from the
subthreshold-to-strong inversion transition region of MOSFETs. It uses an auxiliary operator …