Survey on combinatorial register allocation and instruction scheduling

RC Lozano, C Schulte - ACM Computing Surveys (CSUR), 2019 - dl.acm.org
Register allocation (mapping variables to processor registers or memory) and instruction
scheduling (reordering instructions to increase instruction-level parallelism) are essential …

Register allocation by puzzle solving

FM Quintão Pereira, J Palsberg - Proceedings of the 29th ACM SIGPLAN …, 2008 - dl.acm.org
We show that register allocation can be viewed as solving a collection of puzzles. We model
the register file as a puzzle board and the program variables as puzzle pieces; pre-coloring …

goSLP: globally optimized superword level parallelism framework

C Mendis, S Amarasinghe - Proceedings of the ACM on Programming …, 2018 - dl.acm.org
Modern microprocessors are equipped with single instruction multiple data (SIMD) or vector
instruction sets which allow compilers to exploit superword level parallelism (SLP), a type of …

Combinatorial register allocation and instruction scheduling

RC Lozano, M Carlsson, GH Blindell… - ACM Transactions on …, 2019 - dl.acm.org
This article introduces a combinatorial optimization approach to register allocation and
instruction scheduling, two central compiler problems. Combinatorial optimization has the …

Rl4real: Reinforcement learning for register allocation

S VenkataKeerthy, S Jain, A Kundu… - Proceedings of the …, 2023 - dl.acm.org
We aim to automate decades of research and experience in register allocation, leveraging
machine learning. We tackle this problem by embedding a multi-agent reinforcement …

An integer programming framework for optimizing shared memory use on GPUs

W Ma, G Agrawal - Proceedings of the 19th international conference on …, 2010 - dl.acm.org
General purpose computing using GPUs is becoming increasingly popular, because of
GPU's extremely favorable performance/price ratio. Like standard processors, GPUs also …

A fast MILP solver for high-level synthesis based on heuristic model reduction and enhanced branch and bound algorithm

M Mirhosseini, M Fazlali, MK Fallah, JA Lee - The Journal of …, 2023 - Springer
Modeling high-level synthesis (HLS) as mixed integer linear programming (MILP) affords the
opportunity to integrate constraints and optimization objectives of hardware design in the …

[PDF][PDF] The design and implementation of a non-iterative range analysis algorithm on a production compiler

D do Couto Teixeira, FMQ Pereira - SBLP. SBC, 2011 - homepages.dcc.ufmg.br
This paper presents the first implementation of a non-iterative range analysis algorithm in a
production compiler. Discrete range analyses try to discover the intervals of values that may …

[PDF][PDF] Titre: A Study of Spilling and Coalescing in Register Allocation as Two Separate Phases

MF BOUCHEZ - 2009 - Citeseer
The goal of register allocation is to assign the variables of a program to the registers or to
spill them to memory whenever there are no register left. Since memory is much slower than …

Speed and precision in range analysis

VHS Campos, RE Rodrigues, IR de Assis Costa… - … Symposium, SBLP 2012 …, 2012 - Springer
Range analysis is a compiler technique that determines statically the lower and upper
values that each integer variable from a target program may assume during this program's …