String analysis via automata manipulation with logic circuit representation

HE Wang, TL Tsai, CH Lin, F Yu, JHR Jiang - Computer Aided Verification …, 2016 - Springer
Many severe security vulnerabilities in web applications can be attributed to string
manipulation mistakes, which can often be avoided through formal string analysis. String …

A symbolic model checking approach to the analysis of string and length constraints

HE Wang, SY Chen, F Yu, JHR Jiang - Proceedings of the 33rd ACM …, 2018 - dl.acm.org
Strings with length constraints are prominent in software security analysis. Recent
endeavors have made significant progress in developing constraint solvers for strings and …

Retiming and resynthesis: A complexity perspective

JHR Jiang, RK Brayton - … aided design of integrated circuits and …, 2006 - ieeexplore.ieee.org
Transformations using retiming and resynthesis operations are the most important and
practical (if not the only) techniques used in optimizing synchronous hardware systems …

Detecting malicious logic through structural checking

SC Smith, J Di - 2007 IEEE Region 5 Technical Conference, 2007 - ieeexplore.ieee.org
Hardware is just as susceptible as software to" hacker attacks", through inclusion of
malicious logic; and the consequences of such an attack could be disastrous! The impact of …

Formal Verification of Fault-Tolerant Hardware Designs

L Entrena, AJ Sánchez-Clemente… - IEEE …, 2023 - ieeexplore.ieee.org
Digital circuits for space applications can suffer from operation failures due to radiation
effects. Error detection and mitigation techniques are widely accepted solutions to improve …

Bounded sequence testing from deterministic finite state machines

F Ipate - Theoretical Computer Science, 2010 - Elsevier
The W-andWp-methods are the basis for conformance testing from a deterministic finite state
machine (DFSM) when the conformance relation considered is equivalence. However, many …

Arithmetic transforms for compositions of sequential and imprecise datapaths

K Radecka, Z Zilic - … Transactions on Computer-Aided Design of …, 2006 - ieeexplore.ieee.org
This paper addresses the issue of obtaining compact canonical representations of datapath
circuits with sequential elements for the purpose of equivalence checking and component …

Mining complex boolean expressions for sequential equivalence checking

N Goel, MS Hsiao, N Ramakrishnan… - 2010 19th IEEE Asian …, 2010 - ieeexplore.ieee.org
We propose a novel technique to mine powerful and generalized boolean relations among
flip-flops in a sequential circuit for sequential equivalence checking. In contrast to traditional …

Hardware threat: The challenge of information security

Q Li, H Gao, B Xu, Z Jiao - 2008 International Symposium on …, 2008 - ieeexplore.ieee.org
As the technology of network has been developing, the safety of network is concerned by
more and more people. The technology of information security comes about as a new field …

SEChecker: A Sequential Equivalence Checking Framework Based on th Invariants

F Lu, KT Cheng - IEEE Transactions on Very Large Scale …, 2009 - ieeexplore.ieee.org
In recent years, considerable research efforts have been devoted to utilizing circuit structural
information to improve the efficiency of Boolean satisfiability (SAT) solving, resulting in …