High-resolution hyperspectral imaging via matrix factorization

R Kawakami, Y Matsushita, J Wright, M Ben-Ezra… - CVPR …, 2011 - ieeexplore.ieee.org
Hyperspectral imaging is a promising tool for applications in geosensing, cultural heritage
and beyond. However, compared to current RGB cameras, existing hyperspectral cameras …

Advanced computer arithmetic design

MJ Flynn, SF Oberman - 2001 - philpapers.org
Innovative techniques and cutting-edge research in computer arithmetic design Computer
arithmetic is a fundamental discipline that drives many modern digital technologies. High …

The sum-absolute-difference motion estimation accelerator

S Vassiliadis, EA Hakkennes, J Wong… - … Conference (Cat. No …, 1998 - ieeexplore.ieee.org
We investigate the Sum Absolute Difference (SAD) operation, an operation frequently used
by a number of algorithms for digital motion estimation. For such operation, we propose a …

[HTML][HTML] A modular technique of Booth encoding and Vedic multiplier for low-area and high-speed applications

CM Kalaiselvi, RS Sabeenian - Scientific Reports, 2023 - nature.com
A technique for efficiently multiplying two signed numbers using limited area and high speed
is presented in this paper. This work uses both the Booth and Vedic multiplication sutra …

A 16-bit by 16-bit MAC design using fast 5: 3 compressor cells

O Kwon, K Nowka, EE Swartzlander - … systems for signal, image and video …, 2002 - Springer
2 counters and 4: 2 compressors have been widely used for multiplier implementations. In
this paper, a fast 5: 3 compressor is derived for high-speed multiplier implementations. The …

Improved 64-bit radix-16 booth multiplier based on partial product array height reduction

E Antelo, P Montuschi… - IEEE Transactions on …, 2016 - ieeexplore.ieee.org
In this paper, we describe an optimization for binary radix-16 (modified) Booth recoded
multipliers to reduce the maximum height of the partial product columns to [n/4] for n= 64-bit …

An FPGA implementation guide for some different types of serial–parallel multiplier structures

MA Ashour, HI Saleh - Microelectronics Journal, 2000 - Elsevier
The multiplier is one of the most important components in the computing and reconfigurable
computing systems, especially in the field of digital signal processing (DSP). Hence, in this …

Comparison of single-and dual-pass multiply-add fused floating-point units

RM Jessani, M Putrino - IEEE Transactions on Computers, 1998 - ieeexplore.ieee.org
Low power, low cost, and high performance factors dictate the design of many
microprocessors targeted to the low power computing market. The floating point unit …

FPU implementations with denormalized numbers

EM Schwarz, M Schmookler… - IEEE Transactions on …, 2005 - ieeexplore.ieee.org
Denormalized numbers are the most difficult type of numbers to implement in floating-point
units. They are so complex that certain designs have elected to handle them in software …

A 16-bit/spl times/16-bit MAC design using fast 5: 2 compressors

O Kwon, K Nowka… - … Conference on Application …, 2000 - ieeexplore.ieee.org
3: 2 counters and/or 4: 2 compressors have been widely used for multiplier implementations.
In this paper, a new logical decomposition is derived for fast 5: 2 compressor and is …