Wet bottling process for small diameter deep trench capacitors
RH Arndt, BA Khan, BY Kim, X Wang - US Patent 9,406,683, 2016 - Google Patents
A method including forming a deep trench in a semiconductor-on-insulator substrate
including an SOI layer directly on top of a buried oxide layer directly on top of a base …
including an SOI layer directly on top of a buried oxide layer directly on top of a base …
Integrated circuit having memory array including ECC and column redundancy and method of operating same
AP Singh - US Patent 8,402,326, 2013 - Google Patents
An integrated circuit device comprising a memory cell array having a plurality of memory
cells arranged in a matrix of rows and columns; multiplexer circuitry, coupled to the memory …
cells arranged in a matrix of rows and columns; multiplexer circuitry, coupled to the memory …
Multi-bit memory cell having electrically floating body transistor, and method of programming and reading same
S Okhonin, E Carman, ME Jones - US Patent 7,542,345, 2009 - Google Patents
There are many inventions described herein as well as many aspects and embodiments of
those inventions, for example, multi-bit memory cell and circuitry and techniques for reading …
those inventions, for example, multi-bit memory cell and circuitry and techniques for reading …
Data storage device and refreshing method for use with such device
P Fazan, S Okhonin - US Patent 7,170,807, 2007 - Google Patents
(57) ABSTRACT A data storage device such as a DRAM memory having a plurality of data
storage cells 10 is disclosed. Each data storage cell 10 has a physical parameter which …
storage cells 10 is disclosed. Each data storage cell 10 has a physical parameter which …
Read circuitry for an integrated circuit having memory cells and/or a memory cell array, and method of operating same
P Bauser - US Patent 7,957,206, 2011 - Google Patents
(*) Notice: Subject to any disclaimer, the term of this “Memory Design Using a One-Transistor
GainCell on SOI, IEEE patent is extended or adjusted under 35 J 1 of Soli ournal of Solid …
GainCell on SOI, IEEE patent is extended or adjusted under 35 J 1 of Soli ournal of Solid …
Single transistor memory cell
S Okhonin, M Nagoga - US Patent 8,014,195, 2011 - Google Patents
US PATENT DOCUMENTS 3.439, 214. A 4, 1969 Kabell 3,997,799 A 12, 1976 Baker
4,032.947 A 6, 1977 Kesel et al. 4,250,569 A 2, 1981 Sasaki et al. 4,262,340 A 4, 1981 …
4,032.947 A 6, 1977 Kesel et al. 4,250,569 A 2, 1981 Sasaki et al. 4,262,340 A 4, 1981 …
Memory cell having an electrically floating body transistor and programming technique therefor
S Okhonin, M Nagoga - US Patent 7,476,939, 2009 - Google Patents
(57) ABSTRACT A memory cell comprising an electrically floating body tran sistor including
a source region, a drain region, a body region disposed therebetween, wherein the body …
a source region, a drain region, a body region disposed therebetween, wherein the body …
Memory array having a programmable word length, and method of operating same
E Carman - US Patent 7,492,632, 2009 - Google Patents
6,466,511 B2 10/2002 Fujita et al. 4,791,610 A 12/1988 Takemae 6.479, 862 B1 1 1/2002
King et al. 4.954, 989 A 9, 1990 Auberton-Herve et al. 6,492.211 B1 12/2002 Divakaruni et …
King et al. 4.954, 989 A 9, 1990 Auberton-Herve et al. 6,492.211 B1 12/2002 Divakaruni et …
Semiconductor device
P Fazan, S Okhonin - US Patent 6,969,662, 2005 - Google Patents
A semiconductor device, such as a memory device or radiation detector, is disclosed, in
which data storage cells are formed on a substrate 13. Each of the data storage cells …
which data storage cells are formed on a substrate 13. Each of the data storage cells …
Bipolar reading technique for a memory cell having an electrically floating body transistor
S Okhonin, M Nagoga - US Patent 7,477,540, 2009 - Google Patents
US PATENT DOCUMENTS 6.424, 016 B1 7/2002 Houston 6,429,477 B1 8/2002
Mandelman et al. 4,262,340 A 4, 1981 Sasaki et al. 6,440,872 B1 8/2002 Mandelman et al …
Mandelman et al. 4,262,340 A 4, 1981 Sasaki et al. 6,440,872 B1 8/2002 Mandelman et al …