A nonvolatile memory system, a nonvolatile memory controller and a method for reducing
latency of a memory controller are disclosed. Upon the occurrence of one or more of an …

(57) ABSTRACT A nonvolatile memory controller to recover encoded data by performing a
hard-decision inner error correction code decoding and an outer error correction code …

A nonvolatile memory storage controller for delivering log likelihood ratios (LLRs) to a low-
density parity check (LDPC) decoder for use in the decoding of an LDPC encoded …

Abstract A Solid State Drive (SSD) that includes a host connector receptacle for connecting
to a host computer, a plurality of NAND devices and a nonvolatile memory controller. The …

(57) ABSTRACT A nonvolatile memory controller may recover encoded data using the outer
error correction code of the encoded data if it is determined that a correction capacity of the …

A low-density parity check (LDPC) decoder is provided for decoding low-density parity check
(LDPC) encoded data wherein the processing order of the layers of the LDPC parity check …

A nonvolatile memory storage controller is provided for delivering log likelihood ratios
(LLRs) to a low-density parity check (LDPC) decoder for use in the decoding of an LDPC …

-1145 bit errors in the data unit does not exceed an error correction capacity of the error
correction code. Otherwise, the data storage device generates a modified data unit based on …

A system and method reading, accumulating and processing soft information for use in
LDPC decoding. In accordance with the present invention, an LDPC decoder includes …

A nonvolatile memory storage controller is provided for delivering log likelihood ratios
(LLRs) to a low-density parity check (LDPC) decoder for use in the decoding of an LDPC …