Interconnect structures and methods for forming same
CE Uzoh, LW Mirkarimi - US Patent 11,195,748, 2021 - Google Patents
US11195748B2 - Interconnect structures and methods for forming same - Google Patents
US11195748B2 - Interconnect structures and methods for forming same - Google Patents …
US11195748B2 - Interconnect structures and methods for forming same - Google Patents …
Advanced through substrate via metallization in three dimensional semiconductor integration
DC Edelstein, CC Yang - US Patent 10,312,181, 2019 - Google Patents
A method providing a high aspect ratio through substrate via in a substrate is described. The
through substrate via has vertical sidewalls and a horizontal bottom. The substrate has a …
through substrate via has vertical sidewalls and a horizontal bottom. The substrate has a …
Advanced through substrate via metallization in three dimensional semiconductor integration
DC Edelstein, CC Yang - US Patent 10,396,012, 2019 - Google Patents
ABSTRACT A method providing a high aspect ratio through substrate via in a substrate is
described. The through substrate via has vertical sidewalls and a horizontal bottom. The …
described. The through substrate via has vertical sidewalls and a horizontal bottom. The …
Advanced through substrate via metallization in three dimensional semiconductor integration
DC Edelstein, CC Yang - US Patent 10,396,013, 2019 - Google Patents
An advanced through silicon via structure for is described. The device includes a substrate
including integrated circuit devices. A high aspect ratio through substrate via is disposed in …
including integrated circuit devices. A high aspect ratio through substrate via is disposed in …
Contact plug with impurity variation
WU Chung-Chiang, HW Tsau, CC Lee… - US Patent …, 2022 - Google Patents
A method includes forming an opening in a dielectric layer, depositing a seed layer in the
opening, wherein first portions of the seed layer have a first concentration of impurities …
opening, wherein first portions of the seed layer have a first concentration of impurities …
Semiconductor device and method
WU Chung-Chiang, HW Tsau, CC Lee… - US Patent …, 2020 - Google Patents
(57) ABSTRACT A method includes forming an opening in a dielectric layer, depositing a
seed layer in the opening, wherein first portions of the seed layer have a first concentration …
seed layer in the opening, wherein first portions of the seed layer have a first concentration …
Atomic layer etching of tungsten for enhanced tungsten deposition fill
CS Lai, KJ Kanarik, S Tan… - US Patent App. 17 …, 2021 - Google Patents
US20210305059A1 - Atomic layer etching of tungsten for enhanced tungsten deposition fill
- Google Patents US20210305059A1 - Atomic layer etching of tungsten for enhanced …
- Google Patents US20210305059A1 - Atomic layer etching of tungsten for enhanced …
Contact plug with impurity variation
WU Chung-Chiang, HW Tsau, CC Lee… - US Patent …, 2024 - Google Patents
A method includes forming an opening in a dielectric layer, depositing a seed layer in the
opening, wherein first portions of the seed layer have a first concentration of impurities …
opening, wherein first portions of the seed layer have a first concentration of impurities …
Conformal titanium nitride-based thin films and methods of forming same
N Mukherjee, HY Kim, J Mack, JS Heo… - US Patent App. 17 …, 2022 - Google Patents
Inventors: Niloy Mukherjee, San Ramon, CA (US); Hae Young Kim, San Jose, CA (US); Jerry
Mack, San Jose, CA (US); Jae Seok Heo, Dub CA (US); Sung-Hoon Jung, Santa Clara, CA …
Mack, San Jose, CA (US); Jae Seok Heo, Dub CA (US); Sung-Hoon Jung, Santa Clara, CA …
Contact plug with impurity variation
WU Chung-Chiang, HW Tsau, CC Lee… - US Patent …, 2023 - Google Patents
A method includes forming an opening in a dielectric layer, depositing a seed layer in the
opening, wherein first portions of the seed layer have a first concentration of impurities …
opening, wherein first portions of the seed layer have a first concentration of impurities …