Copper interconnection structure incorporating a metal seed layer

DC Edelstein, JME Harper, CK Hu, AH Simon… - US Patent …, 2001 - Google Patents
BACKGROUND OF THE INVENTION The technology of making interconnections to provide
for vias, lines and other recesses in semiconductor chip structures,? at panel displays, and …

Copper interconnection structure incorporating a metal seed layer

DC Edelstein, JME Harper, CK Hu, AH Simon… - US Patent …, 2002 - Google Patents
BACKGROUND OF THE INVENTION The technology of making interconnections to provide
for vias, lines and other recesses in semiconductor chip structures,? at panel displays, and …

Articles for polishing semiconductor substrates

S Li, LY Chen, A Duboust - US Patent 7,059,948, 2006 - Google Patents
800 plurality of grooves disposed in the polishing Surface. The article of manufacture may
be used in a processing system. The article of manufacture may be used in a method for …

Methods to form metal lines using selective electrochemical deposition

Q Shang, JM White, RZ Bachrach, KS Law - US Patent 6,887,776, 2005 - Google Patents
Methods are provided for forming a transistor for use in an active matrix liquid crystal display
(AMLCD). In one aspect a method is provided for processing a substrate including providing …

Capped copper electrical interconnects

MS Farooq, S Kaja, ED Perfecto, GE White - US Patent 5,898,222, 1999 - Google Patents
The present invention relates generally to a new structure and method for capped copper
electrical interconnects. More particularly, the invention encompasses a novel structure in …

Barrier-less metal seed stack and contact

M Agrawal, SB Rim, M Cudzinovic - US Patent App. 15/064,488, 2016 - Google Patents
Approaches for forming barrier-less seed Stacks and contacts are described. In an example,
a solar cell includes a substrate and a conductive contact disposed on the Substrate. The …

Formation of a masking layer on a dielectric region to facilitate formation of a capping layer on electrically conductive regions separated by the dielectric region

DE Lazovsky, SG Malhotra, TR Boussie - US Patent 7,390,739, 2008 - Google Patents
(57) ABSTRACT A masking layer is formed on a dielectric region of an elec tronic device so
that, during Subsequent formation of a cap ping layer on electrically conductive regions of …

Method for manufacturing interconnect structure

MT Chen, HJ Lin, CW Lin, MD Cheng… - US Patent …, 2021 - Google Patents
A conductive interconnect structure includes a contact pad; a conductive body connected to
the contact pad at a first end; and a conductive layer positioned on a second end of the …

Capping of metal interconnects in integrated circuit electronic devices

E Yakobson, R Hurtubise, C Witt, Q Chen - US Patent 7,393,781, 2008 - Google Patents
4,122.215 A 10/1978 Vratny 4,692,349 A 9/1987 Georgiou et al. A multilayer metal cap over
a metal-filled interconnect fea 4,770,899 A 9, 1988 Zeller ture in a dielectric layer for …

Method of forming embedded copper interconnections and embedded copper interconnection structure

N Ogure, H Inoue - US Patent 6,147,408, 2000 - Google Patents
It is therefore an object of the present invention to provide a method of forming embedded
interconnections of copper While effectively preventing an exposed surface of an the …