This paper describes Trio, a programmable chipset used in Juniper Networks' MX-series
routers and switches. Trio's architecture is based on a multi-threaded programmable packet …

As multi-core architectures with Thread-Level Speculation (TLS) are becoming better
understood, it is important to focus on TLS compilation. TLS compilers are interesting in that …

5.430, 874 A 7, 1995 Kumazaki et al. 5.432, 848 A 7, 1995 Butter et al. 5,446,906 A 8, 1995
Kardach et al. received from the network to the memory. The system includes a processor …

More fundamental than IP lookups and packet classification in routers is the extraction of
fields such as IP Dest and TCP Ports that determine packet forwarding. While parsing of …

Details a real-world product that applies a cutting-edge multi-core architecture Increasingly
demanding modern applications—such as those used in telecommunications networking …

A system including a storage processing device with an input/output module. The
input/output module has port processors to receive and transmit network traffic. The …

The gap between CPU and networking speeds has motivated the development of
SmartNICs for near-network processing. Recent work has shown that many network …

We present PacLang: an imperative, concurrent, linearly-typed language designed for
expressing packet processing applications. PacLang's linear type system ensures that no …

Network processors (NPs) typically contain multiple concurrent processing cores. State-of-
the-art programming techniques for NPs are invariably low-level, requiring programmers to …

To provide a variety of new and advanced communications services, computer networks are
required to perform increasingly complex packet processing. This processing typically takes …