Past challenges and the future of discrete event simulation

AJ Collins, F Sabz Ali Pour… - The Journal of Defense …, 2023 - journals.sagepub.com
The American scientist Carl Sagan once said:“You have to know the past to understand the
present.” We argue that having a meaningful dialogue on the future of simulation requires a …

A novel, highly integrated simulator for parallel and distributed systems

N Tampouratzis, I Papaefstathiou, A Nikitakis… - ACM Transactions on …, 2020 - dl.acm.org
In an era of complex networked parallel heterogeneous systems, simulating independently
only parts, components, or attributes of a system-under-design is a cumbersome, inaccurate …

Scalable performance prediction of codes with memory hierarchy and pipelines

G Chennupati, N Santhi, S Eidenbenz - Proceedings of the 2019 ACM …, 2019 - dl.acm.org
We present the Analytical Memory Model with Pipelines (AMMP) of the Performance
Prediction Toolkit (PPT). PPT-AMMP takes high-level source code and hardware …

Enabling demand response for hpc systems through power capping and node scaling

K Ahmed, J Liu, K Yoshii - … conference on smart city; IEEE 4th …, 2018 - ieeexplore.ieee.org
Demand response is an increasingly popular program ensuring power grid stability during a
sudden surge in power demand. We expect high-performance computing (HPC) systems to …

Machine learning–enabled scalable performance prediction of scientific codes

G Chennupati, N Santhi, P Romero… - ACM Transactions on …, 2021 - dl.acm.org
Hardware architectures become increasingly complex as the compute capabilities grow to
exascale. We present the Analytical Memory Model with Pipelines (AMMP) of the …

Benefits of Optimistic Parallel Discrete Event Simulation for Network-on-Chip Simulation

M Bremer, N Patra, T Nguyen… - 2023 IEEE/ACM 27th …, 2023 - ieeexplore.ieee.org
The end of Moore's law has placed a two-fold demand on hardware simulation. Firstly,
efficient co-design requires fast simulation of hardware systems in order to vet proposed …

3D-stacked memory for shared-memory multithreaded workloads

S Bhattacharya, H González-Vélez - 2020 - norma.ncirl.ie
This paper aims to address the issue of CPU-memory intercommunication latency with the
help of 3D stacked memory. We propose a 3D-stacked memory configuration, where a …

Full-process supported Simulation Platform Framework based on cloud computing and HPC integration

H Wang, J Feng, L Wang - Molecular & Cellular Biomechanics, 2024 - ojs.sin-chn.com
Simulation technology is widely used in many fields, it usually involves three processes,(i)
pre-process,(ii) analysis solver, and (iii) post-process. Simulation calculations require a …

Co-simulation of hardware RTL and software system using FMI

MH Quraishi, HS Sarjoughian… - 2018 Winter Simulation …, 2018 - ieeexplore.ieee.org
Software-hardware co-design enabled with co-simulation is useful for building embedded
computing systems. Indispensable to design is developing hardware and software …

Fit Fly: A Case Study on Interconnect Innovation through Parallel Simulation

N McGlohon, N Wolfe, M Mubarak… - Proceedings of the 2019 …, 2019 - dl.acm.org
To meet the demand for exascale-level performance from high-performance computing
(HPC) interconnects, many system architects are turning to simulation results for accurate …