A survey on compiler autotuning using machine learning

AH Ashouri, W Killian, J Cavazos, G Palermo… - ACM Computing …, 2018 - dl.acm.org
Since the mid-1990s, researchers have been trying to use machine-learning-based
approaches to solve a number of different compiler optimization problems. These …

Ithemal: Accurate, portable and fast basic block throughput estimation using deep neural networks

C Mendis, A Renda, S Amarasinghe… - … on machine learning, 2019 - proceedings.mlr.press
Predicting the number of clock cycles a processor takes to execute a block of assembly
instructions in steady state (the throughput) is important for both compiler designers and …

Self-optimizing memory controllers: A reinforcement learning approach

E Ipek, O Mutlu, JF Martínez, R Caruana - ACM SIGARCH Computer …, 2008 - dl.acm.org
Efficiently utilizing off-chip DRAM bandwidth is a critical issuein designing cost-effective,
high-performance chip multiprocessors (CMPs). Conventional memory controllers deliver …

Milepost gcc: Machine learning enabled self-tuning compiler

G Fursin, Y Kashnikov, AW Memon, Z Chamski… - International journal of …, 2011 - Springer
Tuning compiler optimizations for rapidly evolving hardware makes porting and extending
an optimizing compiler for each new platform extremely challenging. Iterative optimization is …

Predicting unroll factors using supervised classification

M Stephenson, S Amarasinghe - International symposium on …, 2005 - ieeexplore.ieee.org
Compilers base many critical decisions on abstracted architectural models. While recent
research has shown that modeling is effective for some compiler problems, building …

Automatic feature generation for machine learning--based optimising compilation

H Leather, E Bonilla, M O'boyle - ACM Transactions on Architecture and …, 2014 - dl.acm.org
Recent work has shown that machine learning can automate and in some cases outperform
handcrafted compiler optimisations. Central to such an approach is that machine learning …

[图书][B] The compiler design handbook: optimizations and machine code generation

YN Srikant, P Shankar - 2002 - taylorfrancis.com
The widespread use of object-oriented languages and Internet security concerns are just the
beginning. Add embedded systems, multiple memory banks, highly pipelined units …

GRANITE: A graph neural network model for basic block throughput estimation

O Sýkora, PM Phothilimthana, C Mendis… - 2022 IEEE …, 2022 - ieeexplore.ieee.org
Analytical hardware performance models yield swift estimation of desired hardware
performance metrics. However, developing these analytical models for modern processors …

uiCA: Accurate throughput prediction of basic blocks on recent Intel microarchitectures

A Abel, J Reineke - Proceedings of the 36th ACM International …, 2022 - dl.acm.org
Performance models that statically predict the steady-state throughput of basic blocks on
particular microarchitectures, such as IACA, Ithemal, llvm-mca, OSACA, or CQA, can guide …

Rollout strategies for sequential fault diagnosis

F Tu, KR Pattipati - IEEE Transactions on Systems, Man, and …, 2003 - ieeexplore.ieee.org
Test sequencing is a binary identification problem wherein one needs to develop a minimal
expected cost testing procedure to determine which one of a finite number of possible failure …