Verilog is a hardware description language (HDL) that has become an industry-standard
HDL of IEEE. Multithreaded discrete event simulation language (MDESL) is a Verilog-like …

This paper provides an overview of Jifeng He's academic achievements while at Oxford
University in the UK, and later in Macau and Shanghai, together with his legacy …

The deductive verification of computer programs helps ascertain the absence of errors for all
possible inputs and executions. Computer programs can be written in a plethora of …

A reliable technique for deductive program verification should be proven sound with respect
to the semantics of the programming language. For each different language, the construction …

Hardware architectures like x86 and ARM provide relaxed memory models for efficiency
reasons. The revised ARMv8 architecture is multi-copy atomic (MCA), which brings relaxed …

Modern multiprocessors deploy a variety of weak memory models (WMMs). Total Store
Order (TSO) is a widely-used weak memory model in SPARC implementations and x86 …

The chapter introduces probabilistic CSP#(PCSP#) as a formal language for modeling
probabilistic systems, emphasizing its foundational role in concurrent and parallel …

Abstract Cyber-Physical systems (CPS), containing discrete behaviors of the cyber and
continuous behaviors of the physical, have gained wide applications in many fields. Since …

Abstract Unifying Theories of Concurrent Programming (UTCP) is a denotational semantics
of shared-variable concurrency, expressed using the notation and methodology of Unifying …

This paper describes work done using formal methods to verify parts of the RTEMS real-time
operating system, as part of an activity sponsored by the European Space Agency to qualify …