Optical interconnects finally seeing the light in silicon photonics: Past the hype
Electrical interconnects are becoming a bottleneck in the way towards meeting future
performance requirements of integrated circuits. Moore's law, which observes the doubling …
performance requirements of integrated circuits. Moore's law, which observes the doubling …
Networks on chips: structure and design methodologies
The next generation of multiprocessor system on chip (MPSoC) and chip multiprocessors
(CMPs) will contain hundreds or thousands of cores. Such a many‐core system requires …
(CMPs) will contain hundreds or thousands of cores. Such a many‐core system requires …
[图书][B] Vom Musikalisch-Schönen: Ein Beitrag zur Revision der Ästhetik der Tonkunst
E Hanslick - 1902 - books.google.com
Vorwort. lu der achten Auflage (1891) dieser zuerst im Jahre 1854 erschienenen Schrift war
nichts weiter neu, als das passendere Format und die geschmackvollere Ausstattung …
nichts weiter neu, als das passendere Format und die geschmackvollere Ausstattung …
A survey of emerging interconnects for on-chip efficient multicast and broadcast in many-cores
Networks-on-chip (NoC) have emerged to tackle different on-chip communication
challenges and can satisfy different demands in terms of performance, cost and reliability …
challenges and can satisfy different demands in terms of performance, cost and reliability …
NoC with near-ideal express virtual channels using global-line communication
As processor core counts increase, networks-on-chip (NoCs) are becoming an increasingly
popular interconnection fabric due to their ability to supply high bandwidth. However, NoCs …
popular interconnection fabric due to their ability to supply high bandwidth. However, NoCs …
A bidirectional NoC (BiNoC) architecture with dynamic self-reconfigurable channel
YC Lan, HA Lin, SH Lo, YH Hu… - IEEE Transactions on …, 2011 - ieeexplore.ieee.org
A bidirectional channel network-on-chip (BiNoC) architecture is proposed to enhance the
performance of on-chip communication. In a BiNoC, each communication channel allows to …
performance of on-chip communication. In a BiNoC, each communication channel allows to …
Cost effective routing techniques in 2D mesh NoC using on-chip transmission lines
Advancements in CMOS technology led to the increase in number of processing cores on a
single chip. Communication between different cores in such multicore systems is facilitated …
single chip. Communication between different cores in such multicore systems is facilitated …
Current-mode full-duplex transceiver for lossy on-chip global interconnects
N Wary, P Mandal - IEEE Journal of Solid-State Circuits, 2017 - ieeexplore.ieee.org
This paper presents an energy efficient full-duplex (FD) current-mode transceiver for on-chip
global interconnects. As it shares the same signaling port for transmitting and receiving …
global interconnects. As it shares the same signaling port for transmitting and receiving …
Glocks: Efficient support for highly-contended locks in many-core cmps
JL Abell, J Fern, ME Acacio - 2011 IEEE International Parallel …, 2011 - ieeexplore.ieee.org
Synchronization is of paramount importance to exploit thread-level parallelism on many-core
CMPs. In these architectures, synchronization mechanisms usually rely on shared variables …
CMPs. In these architectures, synchronization mechanisms usually rely on shared variables …
An energy-efficient partition-based XYZ-planar routing algorithm for a wireless network-on-chip
In the current many-core architectures, network-on-chips (NoCs) have been efficiently
utilized as communication backbones for enabling massive parallelism and high degree of …
utilized as communication backbones for enabling massive parallelism and high degree of …