Exploring the Landscape of Phase-Locked Loop Architectures: A Comprehensive Review

D Dutta, SP Tumukunta, NR Sivaraaj… - IEEE Access, 2024 - ieeexplore.ieee.org
This paper aims to explore diverse landscape of Phase Locked Loops (PLLs), offering a
comprehensive categorization and in-depth analysis of their underlying working principles …

Design of a fully integrated VHF CP‐PLL frequency synthesizer with an all‐digital defect‐oriented built‐in self‐test

B Kommey, KO Boateng, J Yankey… - The Journal of …, 2023 - Wiley Online Library
This paper presents the design of an on‐chip charge pump phase‐locked loop (CP‐PLL)
with a fully digital defect‐oriented built‐in self‐test (BIST) for very‐high frequency (VHF) …

Asymmetric 5.5 GHz Three-Stage Voltage-Controlled Ring-Oscillator in 65 nm CMOS Technology

G Ciarpi, D Monda, M Mestice, D Rossi, S Saponara - Electronics, 2023 - mdpi.com
The current trend of increasing the complexity of hardware accelerators to improve their
functionality is highlighting the problem of sharing a high-frequency clock signal for all …

Design and Analysis of Two-stage CMOS LCD Buffer Operational Amplifier with Additional Load Capacitance

N Sultana, K Yashwant, M Shivaprasad… - … on Electronics and …, 2022 - ieeexplore.ieee.org
The research paper represents comparative analysis of MOSFET parameters such as Delay,
Phase Margin, Power consumption and Unity Gain Bandwidth (UGB) between pre-layout …

Highly stable signal generation in microwave interferometer using PLLs

JP Chaudhari, B Patel, AV Patel, AD Vala… - Fusion Engineering and …, 2020 - Elsevier
The microwave interferometer is a device that works in the millimeter-wave frequency range,
and it is used to measure the plasma density. The instability in the frequency source at the …

[PDF][PDF] Design of efficient ring VCO using nano scale double gate MOSFET

S Suman - Mody University International Journal of Computing …, 2018 - researchgate.net
In this paper a voltage controlled oscillator (VCO) using MOSFET (Metal Oxide
Semiconductor Field Effect Transistor) and Double Gate (DG) MOSFET are compared and …

Frequency multiplier using phase-locked loop

HG Shettar, S Kotabagi, N Shanbhag… - 2020 IEEE 17th India …, 2020 - ieeexplore.ieee.org
A Phase-Locked Loop (PLL) Frequency multiplier application is been presented in this
paper. The designed PLL is a type-2, order-3 CPPLL with a tuning range of 143-176M Hz …

[PDF][PDF] Design of two stage CMOS comparator with improved accuracy in terms of different parameters

S Suman - Mody University International Journal of Computing …, 2018 - researchgate.net
The well developing industry of electronics is insistent to low power and high speed and less
area ADCs (analog to digital converters). Comparator is device that is especially employed …

A low power wideband varactorless VCO using tunable active inductor

O Faruqe, R Akhter, MT Amin - … Computing Electronics and …, 2020 - telkomnika.uad.ac.id
This paper presents a wideband varactorless voltage controlled oscillator (VCO) based on
tunable active inductor in 90 nm CMOS process which yields a tuning range of 1.22 GHz to …

Optimal Low Power Design Of PLL

S Upadhye, S Kotabagi… - 2024 15th International …, 2024 - ieeexplore.ieee.org
This paper elucidates the architectural blueprint and practical execution of a Phase-Locked
Loop (PLL), integrating a Phase Frequency Detector (PFD), Charge Pump (CP), passive low …