Fault and error tolerance in neural networks: A review
C Torres-Huitzil, B Girau - IEEE Access, 2017 - ieeexplore.ieee.org
Beyond energy, the growing number of defects in physical substrates is becoming another
major constraint that affects the design of computing devices and systems. As the underlying …
major constraint that affects the design of computing devices and systems. As the underlying …
Problems and challenges of emerging technology networks− on− chip: A review
AB Achballah, SB Othman, SB Saoud - Microprocessors and Microsystems, 2017 - Elsevier
Abstract Networks− on− chip (NoC) are an alternative to alleviate the problems of legacy
interconnect fabrics. However, many emerging technology NoC are developed and are now …
interconnect fabrics. However, many emerging technology NoC are developed and are now …
Fault-tolerant routing mechanism in 3D optical network-on-chip based on node reuse
The three-dimensional Network-on-Chips (3D NoCs) has become a mature multi-core
interconnection architecture in recent years. However, the traditional electrical lines have …
interconnection architecture in recent years. However, the traditional electrical lines have …
Scalable design methodology and online algorithm for TSV-cluster defects recovery in highly reliable 3D-NoC systems
3D-Network-on-Chips exploit the benefits of Network-on-Chips and 3D-Integrated Circuits
allowing them to be considered as one of the most advanced and auspicious …
allowing them to be considered as one of the most advanced and auspicious …
First-last: a cost-effective adaptive routing solution for TSV-based three-dimensional networks-on-chip
A Charif, A Coelho, M Ebrahimi… - IEEE Transactions …, 2018 - ieeexplore.ieee.org
3D integration opens up new opportunities for future multiprocessor chips by enabling fast
and highly scalable 3D Network-on-Chip (NoC) topologies. However, in an aim to reduce …
and highly scalable 3D Network-on-Chip (NoC) topologies. However, in an aim to reduce …
Roadmap for machine learning based network-on-chip (M/L NoC) technology and its analysis for researchers
K Balamurugan, S Umamaheswaran… - Journal of Physics …, 2022 - iopscience.iop.org
A few decades ago, communication inside the chip is done by transferring signals between
the cores. This conventional method is not worthy because of the increase in latency and …
the cores. This conventional method is not worthy because of the increase in latency and …
FT-DeepNets: Fault-Tolerant Convolutional Neural Networks with Kernel-based Duplication
Deep neural network (deepnet) applications play a crucial role in safety-critical systems
such as autonomous vehicles (AVs). An AV must drive safely towards its destination …
such as autonomous vehicles (AVs). An AV must drive safely towards its destination …
A low-overhead soft–hard fault-tolerant architecture, design and management scheme for reliable high-performance many-core 3D-NoC systems
Abstract The Network-on-Chip (NoC) paradigm has been proposed as a favorable solution
to handle the strict communication requirements between the increasingly large number of …
to handle the strict communication requirements between the increasingly large number of …
TSV-OCT: A scalable online multiple-TSV defects localization for real-time 3-D-IC systems
In order to detect and localize through-silicon-via (TSV) failures in both manufacturing and
operating phases, most of the existing methods use a dedicated testing mechanism with …
operating phases, most of the existing methods use a dedicated testing mechanism with …
Three-dimensional NoC reliability evaluation
Methods, storage mediums, and apparatuses for evaluating the reliability of Three-
Dimensional (3D) Network-on-Chip (NoC) designs are described. The described …
Dimensional (3D) Network-on-Chip (NoC) designs are described. The described …