The high phase noise of ring oscillators has generally discouraged their use in RF synthesis.
This paper introduces an integer-N synthesizer that employs a type-I loop to achieve a wide …

A 1.25 GS/s 6b ADC is implemented in a 0.13 mum digital CMOS process by time-
interleaving two SAR ADCs with 2.5 GHz internal clock frequency that converts 6 bits in 3 …

This paper presents a 900 MHz highly digital transmitter capable of providing band shaped
QPSK/16-QAM modulation for high data-rate applications with high energy efficiency …

This paper explores a new topology of charge-pump PLL intended for ΔΣ-fractional-N
frequency synthesis. Thanks to the adoption of a bang-bang phase detector and a two-path …

An architectural solution for designing a low-reference-spur PLL is proposed. A spur-
frequency boosting block is inserted between the phase-frequency detector and the charge …

This paper proposes a wideband subharmonically injection-locked PLL (SILPLL) with
adaptive injection timing alignment technique. The SILPLL includes three main circuit …

A 4th order RF LC-based ΣΔ ADC clocked at 3.6 GHz and centered at 900 MHz is
presented. A simple design methodology is used to derive a robust architecture with a …

Multiphase local-oscillator (LO) generators have been widely adopted in modern wireless
communication systems. This paper describes the analysis and design of two open-loop …

Due to its architectural simplicity, the direct conversion scheme is attractive for low-cost, low-
complexity and/or reconfigurable transceiver design. Unfortunately, this scheme comes with …

High-speed PLL is highly demanding with the advancement in the VLSI market. PLL
performance gets affected due to bandwidth limitation. This paper presents third-order …