Flexible architectures for cryptographic algorithms—A systematic literature review

M Rashid, M Imran, AR Jafri… - Journal of Circuits …, 2019 - World Scientific
Symmetric and asymmetric cryptographic algorithms are used for a secure transmission of
data over an unsecured public channel. In order to use these algorithms in real-time …

[HTML][HTML] An efficient AES implementation using FPGA with enhanced security features

H Zodpe, A Sapkal - Journal of King Saud University-Engineering Sciences, 2020 - Elsevier
Data transferred in an electronic way is vulnerable to attacks. With an aim to protect data for
secure communication, a new Hybrid non pipelined Advanced Encryption Standard (AES) …

Area-efficient nano-AES implementation for Internet-of-Things devices

K Shahbazi, SB Ko - IEEE Transactions on Very Large Scale …, 2020 - ieeexplore.ieee.org
Due to the fast-growing number of connected tiny devices to the Internet of Things (IoT),
providing end-to-end security is vital. Therefore, it is essential to design the cryptosystem …

Comparative analysis of flexible cryptographic implementations

M Rashid, M Imran, AR Jafri - 2016 11th International …, 2016 - ieeexplore.ieee.org
Flexible hardware implementations of cryptographic algorithms in the real time applications
have been frequently proposed. This paper classifies the state-of-the-art research practices …

An ultra-high throughput and fully pipelined implementation of AES algorithm on FPGA

A Soltani, S Sharifian - Microprocessors and Microsystems, 2015 - Elsevier
Abstract AES (Advanced Encryption Standard) is one of the most popular symmetric key
encryption algorithms. S-box (Substitution block) is main block in AES. In contrast to many …

FPGA implementation of hardware architecture with AES encryptor using sub-pipelined S-box techniques for compact applications

C Arul Murugan, P Karthigaikumar… - Automatika: časopis za …, 2020 - hrcak.srce.hr
Sažetak Advanced Encryption Standard (AES) is a thriving cryptographic algorithm that can
be utilized to guarantee security in electronic information. It remains to uphold to be resistive …

High throughput and area‐efficient FPGA implementation of AES for high‐traffic applications

K Shahbazi, SB Ko - IET Computers & Digital Techniques, 2020 - Wiley Online Library
This study presents a high throughput field‐programmable gate array (FPGA)
implementation of advanced encryption standard‐128 (AES‐128). AES is a well‐known …

FPGA based fast and high-throughput 2-slow retiming 128-bit AES encryption algorithm

RR Farashahi, B Rashidi, SM Sayedi - Microelectronics journal, 2014 - Elsevier
This paper presents a high throughput digital design of the 128-bit Advanced Encryption
Standard (AES) algorithm based on the 2-slow retiming technique on FPGA. The C-slow …

New data-hiding algorithm based on adaptive neural networks with modified particle swarm optimization

NN El-Emam - Computers & Security, 2015 - Elsevier
A new steganography algorithm based on five protection layers has been suggested in this
paper for embedding a large amount of secret messaging in a color image, as represented …

A novel algorithm for colour image steganography using a new intelligent technique based on three phases

NN El-Emam, M Al-Diabat - Applied Soft Computing, 2015 - Elsevier
A three-phase intelligent technique has been constructed to improve the data-hiding
algorithm in colour images with imperceptibility. The first phase of the learning system (LS) …