High-voltage thin-SOI LDMOS with ultralow ON-resistance and even temperature characteristic
An ultralow specific ON-resistance (R ON, sp) thin-silicon-on-insulator (SOI) LDMOS is
proposed. Its ON-state and OFF-state mechanisms and thermal characteristic are …
proposed. Its ON-state and OFF-state mechanisms and thermal characteristic are …
具有分段P 型埋层的Triple-RESURF LDMOS
何乃龙， 许杰， 王浩， 赵景川， 王婷， 朱文明… - …, 2023 - opticsjournal.net
摘要提出了一种具有分段P 型埋层的Triple-RESURF LDMOS (SETR LDMOS).
该结构将传统Triple-RESURF LDMOS (TR LDMOS) 中均匀掺杂的P 埋层漏端一侧做分段处理 …
该结构将传统Triple-RESURF LDMOS (TR LDMOS) 中均匀掺杂的P 埋层漏端一侧做分段处理 …
Dimension effect on breakdown voltage of partial SOI LDMOS
YUE Hu, H Liu, Q Xu, L Wang, J Wang… - IEEE Journal of the …, 2017 - ieeexplore.ieee.org
Dimension effect on breakdown voltage (BV) of lateral double-diffused metal-oxide–
semiconductor field-effect transistor in partial silicon-on-insulator (PSOI) technology is …
semiconductor field-effect transistor in partial silicon-on-insulator (PSOI) technology is …
Improving breakdown performance for novel LDMOS using n+ floating islands in substrate
Y Chen, SD Hu, K Cheng, Y Jiang, J Zhou… - Electronics …, 2016 - Wiley Online Library
A novel lateral double‐diffusion MOS (LDMOS) with n+ floating islands in the substrate (NFI
LDMOS) is proposed. In the NFI LDMOS, a series of n+ floating islands are introduced into …
LDMOS) is proposed. In the NFI LDMOS, a series of n+ floating islands are introduced into …
Analytical model for silicon-on-insulator lateral high-voltage devices using variation of lateral thickness technique
J Yao, Y Guo, M Li, X Huang, H Lin… - Japanese Journal of …, 2015 - iopscience.iop.org
Recently, the variation of lateral thickness (VLT) technique has been proposed as an
effective lateral voltage-sustaining technology. However, no analytical model has been …
effective lateral voltage-sustaining technology. However, no analytical model has been …
Low Specific On-resistance SOI LDMOS Device with P+P-top Layer in the Drift Region
JF Yao, YF Guo, GM Xu, TT Hua, H Lin… - JSTS: Journal of …, 2014 - koreascience.kr
In this paper, a novel low specific on-resistance SOI LDMOS Device with P+ P-top layer in
the drift region is proposed and investigated using a two dimensional device simulator …
the drift region is proposed and investigated using a two dimensional device simulator …
TID-induced breakdown voltage degradation in uniform and linear variable doping SOI p-LDMOSFETs
The breakdown voltage (BVDS) of uniform doping (UD) and linear variable doping (LVD)
silicon-on-insulator (SOI) p-channel laterally diffused metal oxide semiconductor field effect …
silicon-on-insulator (SOI) p-channel laterally diffused metal oxide semiconductor field effect …
Temperature Effects on Resistance of Power Devices
HC You, CY Wu, WL Yang - 2016 International Symposium on …, 2016 - ieeexplore.ieee.org
In recent years, due to the rapid development of integrated circuits, the demand of power
devices is increasing. These power devices are often used in mobile phones, power …
devices is increasing. These power devices are often used in mobile phones, power …
Improving breakdown voltage for a novel SOI LDMOS with a lateral variable doping profile on the top interface of the buried oxide layer
J Jin, S Hu, Y Chen, K Tan, J Luo… - … in Condensed Matter …, 2015 - Wiley Online Library
In order to achieve a high breakdown voltage (BV) for the SOI (Silicon‐On‐Insulator) power
device in high voltage ICs, a novel high voltage n‐channel lateral double‐diffused MOS …
device in high voltage ICs, a novel high voltage n‐channel lateral double‐diffused MOS …
ESD reliability evaluations of the 60-V nLDMOS by the drain-side discrete SCRs
SL Chen, KJ Chen, YC Wu, JM Lin… - … Symposium on Next …, 2016 - ieeexplore.ieee.org
The influences of ESD protection capability and latchup immunity in 60-V high-voltage N-
channel LDMOS transistors by the drain-side discrete and embedded SCR structures are …
channel LDMOS transistors by the drain-side discrete and embedded SCR structures are …